Design a 16-bit register bank consisting 8 registers with two read ports and one

Question

Design a 16-bit register bank consisting 8 registers with two read ports and one write port. Note that, Read operation on each port gives 16 bit data. Write port needs 16 bit data and address (register number) to perform write operation. The write_ enable signal has to remain high during write operation. Register 0 (R0) is always 0 and write operation is forbidden on R0. Reset would to make all the 7 registers to zero. Read or Write operation can be done only at the positive edge of clock cycle. If write and read operation are done on the same clock cycle, reading through port 1 will give the old values. Reading through port 2 will provide the new values. Write a test bench to perform the following tasks and display results. Display the contents of all the registers. Write all the registers and display the values. Read from port I and display. Read from port 2 and display. Write and Read. Read through port 1 and port 2.

Explanation / Answer

machine instruction

P37X ISA

The ISA will will implement in CSE 371/372 is called P37X. It is a simple RISC ISA that resembles a combination of MIPS and LC3. The following analogy is roughly true: P37X is to LC3 as MIPS is to x86.

P37X shares the following features with LC3 (and differences with MIPS):

P37X shares the following features with MIPS (and differences with LC3):

Arithmetic, Logical, and Shifts unused undefined 0000 ddds sstt t000 unused undefined 0000 ddds sstt t001 unused undefined 0000 ddds sstt t010 unused undefined 0000 ddds sstt t011 ADD rd, rs, rt regs[rd] = regs[rs] + regs[rt] 0000 ddds sstt t100 SUB rd, rs, rt regs[rd] = regs[rs] - regs[rt] 0000 ddds sstt t101 MUL rd, rs, rt regs[rd] = regs[rs] * regs[rt] 0000 ddds sstt t110 unused undefined 0000 ddds sstt t111 OR rd, rs, rt regs[rd] = regs[rs] | regs[rt] 0001 ddds sstt t000 NOT rd, rs regs[rd] = ~regs[rs] 0001 ddds ssXX X001 AND rd, rs, rt regs[rd] = regs[rs] & regs[rt] 0001 ddds sstt t010 XOR rd, rs, rt regs[rd] = regs[rs] ^ regs[rt] 0001 ddds sstt t011 SLL rd, rs, rt regs[rd] = regs[rs] << (regs[rt] & 15) 0001 ddds sstt t100 SRL rd, rs, rt regs[rd] = ZEXT(regs[rs] >> (regs[rt] & 15)) 0001 ddds sstt t101 SRA rd, rs, rt regs[rd] = SEXT(regs[rs] >> (regs[rt] & 15)) 0001 ddds sstt t110 unused undefined 0001 ddds sstt t111 Traps and Returns from Trap TRAP imm8 regs[r7] = PC + 1
PC = imm8
PSR[15]=1 0010 XXXX iiii iiii RTT rd PC = regs[rd]
PSR[15] = 0 0011 dddX XXXX XXXX Calls and Jumps JUMP imm12 (label) PC = PC + 1 + SEXT(imm12) 0100 iiii iiii iiii JUMPR rd PC = regs[rd] 0101 dddX XXXX XXXX JSR imm12 (label) regs[r7] = PC + 1
PC = PC + 1 + SEXT(imm12) 0110 iiii iiii iiii JSRR rd regs[r7] = PC + 1
PC = regs[rd] 0111 dddX XXXX XXXX Conditional Branches NOOP PC = PC + 1 1000 XXX0 00XX XXXX BRP rd, imm6 (label) if (regs[rd] > 0) PC = PC + 1 + SEXT(imm6) 1000 ddd0 01ii iiii BRZ rd, imm6 (label) if (regs[rd] == 0) PC = PC + 1 + SEXT(imm6) 1000 ddd0 10ii iiii BRZP rd, imm6 (label) if (regs[rd] >= 0) PC = PC + 1 + SEXT(imm6) 1000 ddd0 11ii iiii BRN rd, imm6 (label) if (regs[rd] < 0) PC = PC + 1 + SEXT(imm6) 1000 ddd1 00ii iiii BRNP rd, imm6 (label) if (regs[rd] != 0) PC = PC + 1 + SEXT(imm6) 1000 ddd1 01ii iiii BRNZ rd, imm6 (label) if (regs[rd] <= 0) PC = PC + 1 + SEXT(imm6) 1000 ddd1 10ii iiii BRNZP rd, imm6 (label) PC = PC + 1 + SEXT(imm6) 1000 ddd1 11ii iiii Constants CONST rd, imm9 regs[rd] = SEXT(imm9) 1001 dddi iiii iiii INC rd, imm9 regs[rd] = regs[rd] + SEXT(imm9) 1010 dddi iiii iiii LEA rd, imm9 (label) regs[rd] = PC + 1 + SEXT(imm9) 1011 dddi iiii iiii Loads and Stores LDR rd, rs, imm6 regs[rd] = mem[regs[rs] + SEXT(imm6)] 1100 ddds ssii iiii STR rd, rs, imm6 mem[regs[rs] + SEXT(imm6)] = regs[rd] 1101 ddds ssii iiii LD rd, imm9 (label) regs[rd] = mem[PC + 1 + SEXT(imm9)] 1110 dddi iiii iiii ST rd, imm9 (label) mem[PC + 1 + SEXT(imm9)] = regs[rd] 1111 dddi iiii iiii

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