A 4-bit up/down binary counter with output Q works as follows: All state changes
ID: 1716531 • Letter: A
Question
A 4-bit up/down binary counter with output Q works as follows: All state changes occur on the rising edge of the CLK input, except the asynchronous clear (ClrN). When ClrN = 0, the counter is reset regardless of the values of the other inputs.
If the LOAD input is 0, the data input D is loaded into the counter.
If the LOAD = ENT = ENP = UP = 1, the counter is incremented.
If the LOAD = ENT = ENP = 1 and UP = 0, the counter is decremented.
If the ENT = UP =1, the carry output (CO) = 1 when the counter is in state 15.
If the ENT = 1 and UP = 0, the carry output (CO) = 1 when the counter is in state 0.
Write a VHDL description of the counter.
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_VHDL is
port( Number: in std_logic_vector(0 to 3);
Clock: in std_logic;
Load: in std_logic;
Reset: in std_logic;
Direction: in std_logic;
Output: out std_logic_vector(0 to 3) );
end Counter_VHDL;
architecture Behavioral of Counter_VHDL is
signal temp: std_logic_vector(0 to 3);
begin
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif ( Clock'event and Clock='1') then
if Load='1' then
temp <= Number;
elsif (Load='0' and Direction='0') then
temp <= temp + 1;
elsif (Load='0' and Direction='1') then
temp <= temp - 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;