A 4-bit register has the following functions depending on the selections bits S1
ID: 2085370 • Letter: A
Question
A 4-bit register has the following functions depending on the selections bits S1 and S2: 1) right shift; 2) left shift; 3) parallel load; 4) reset (cleared). You can name the serial input SIN and the 4 bit parallel input D3,D2,D1, and D0. The 4 bit register outputs are represented by Q3,Q2,Q1, and Q0. Add other inputs /outputs variables as needed. Please keep it simple !!!
4-bit register has the following functions depending on the selection bits S1 and So: 2. A 4-bit register has the following functions depending on the selection bits S1 and So: ) right-shift; 2) left-shift; 3) parallel load; and 4) reset (cleare SIN and the 4-bit parallel input D3, D2, DI and DO. The 4-bit register outputs are represented b d). You can name the serial input 03, 02, 01, and Q0. Add other input/output variable if needed. S1 so 0 1 1 0 Operation Right-shift Left-shift Parallel load ResetExplanation / Answer
Ans) 1) shift right
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
s0=tmp(0);
for i in 1 to 7 loop
tmp (i-1) = tmp(i);
end loop;
tmp(7) = SI;
end if;
end process;
SO = tmp(7);
end archi;
2) shift left
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
s0=tmp(0);
for i in 1 to 7 loop
tmp (i+1) = tmp(i);
end loop;
tmp(7) = SI;
end if;
end process;
SO = tmp(7);
end archi;
3) Parallel load
VHDL code for Parallel In Parallel Out Shift Register
library ieee;
use ieee.std_logic_1164.all;
entity pipo is
port(
clk : in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end pipo;
architecture arch of pipo is
begin
process (clk)
begin
if (CLK'event and CLK='1') then
Q <= D;
end if;
end process;
end arch;
VHDL Code for Serial In Parallel Out Shift Register
library ieee;
use ieee.std_logic_1164.all;
entity pipo is
port(
clk : in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end pipo;
architecture arch of pipo is
begin
process (clk)
begin
if (CLK'event and CLK='1') then
Q <= D;
end if;
end process;
end arch;
VHDL Code for Serial In Parallel Out Shift Register
library ieee;</pre>
<pre>use ieee.std_logic_1164.all;
entity sipo is
port(
clk, clear : in std_logic;
Input_Data: in std_logic;
Q: out std_logic_vector(3 downto 0) );
end sipo;
architecture arch of sipo is
begin
process (clk)
begin
if clear = '1' then
Q <= "0000";
elsif (CLK'event and CLK='1') then
Q(3 downto 1) <= Q(2 downto 0);
Q(0) <= Input_Data;
end if;
end process;
end arch;
4) for reset
library ieee;
use ieee.std_logic_1164.all;
entity USR is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
CLK, RST : in STD_LOGIC;
SIR, SIL : in STD_LOGIC;
S :in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end entity USR;
architecture Behavioral of USR is
begin
process(CLK, RST) is
variable REG : std_logic_vector(3 downto 0);
begin
if (RST = '0') then
reg := (others => '0');
elsif rising_edge(clk) then
case S is
when "11" =>
REG := D;
when "01" =>
REG := SIR & REG(3 downto 1);
when "10" =>
REG := REG(2 downto 0) & SIL;
when others =>
null;
end case;
end if;
Q <= REG;
end process;
end architecture;