Part 1 – 4-bit Serial Adder Develop a VHDL entity declaration for the serial add
ID: 1995833 • Letter: P
Question
Part 1 – 4-bit Serial Adder
Develop a VHDL entity declaration for the serial adder (all ports have to be std_logic and std_logic_vector types).
Implementation details for a 4-bit serial adder entity
inputs:
outputs:
in_a 4 bits
in_b 4 bits
control 2 bits (s1, s0)
clk 1 bit (100ns period)
reset_al 1 bit (asynchronous active low)
Sum 4 bits
carry 1 bit
Implement the serial adder in a structural way only. Your description is to be composed of the following five components and a few internal signals (internal descriptions of all components should use “processes”):
component - 1 bit full_adder (introduces 8 ns delay),
component - d - flip flop with enable and asynchronous reset (introduces 2 ns delay),
component - 2 inputs and gate (introduces 4 ns delay), One of the inputs is to be active low the second one active-high.
two components which describe 4-bit parallel load shift registers: regA and regB (introduce 20 ns delay each). The functionality of the registers has to be exactly the same as 74LS194A – 4-Bit Bi-directional Universal Shift Register.
Note: All registers and flip-flop are rising edge active !
Functional Details (Note: for shift registers: 00: hold; and 11: load; and 01: shift right; see below details):
·On the rising edge of a clk signal, when control is ”11”, the registers are loaded with in_a (regA) and in_b (regB). On the rising edges of a clk, when control is ”01”, the registers are shifted (LSB first) into the 1 bit full adder.
·The full adder’s sum bit is shifted into the register port holding the in_a. After 4 clock rising edges, while the control remains ”01”, the regA register contains the value in_a + in_b and carry should be the corresponding carry out bit.
The output sum is assumed not to be valid until the 4th rising edge of a clk signal after load is set to ’0’.
2)
The testbench will apply all inputs (in_a, in_b, control, clk and reset_al) and verify the outputs, using assert statements to flag errors.
Verification process will apply inputs (in_a, in_b, control and reset_al) and verify the outputs, using assert statements to flag errors. A constant (an array of a record type) will be used to store the values for in_a, in_b, sum and carry. The values to be used for in_a and in_b are as follows:
in_a
in_b
sum
carry
X”0”
X”4”
X”C”
X”E”
X”8”
X”A”
X”F”
X”F”
X”F”
X”1”
X”A”
X”5”
X”2”
‘0’
X”8”
X”7”
Please fill out the rest of the table and include it in your report (use ’hex’ notation). Do not change the result A+5 (see the 6th row of the above table). We intentionally made it wrong.
Your testbench checks the result. If any error occurs, assert statement should give appropriate message. Timing is a crucial thing in your testbench. Remember to reset the circuit before you start a new addition cycle (Explain why it is important in the lab report).
Part 2 – Connect the FSM to the above Serial Adder
1)
The following state machine can be used as a control block for the serial adder designed in the previous lab. The state diagram is given below. It is a Moore machine since outputs depend only on the current state.
Implementation details for a Control Block entity
inputs:
outputs: (ready, reset_SA, s1, s0)
start 1 bits
clk 1 bit
reset_SM 1 bit (asynchronous active low)
control 4 bits
Write a behavioral VHDL description of the state machine. Simulate it.
Synthesize the state machine using DFF and additional gates. Draw the schematic. Name all signals (including internal signals) using the same name as you will use for the structural description.
2)
Connect your serial adder and control block to create the whole design. Write the testbench (see below) to test the new complete design. Output signal ready can be used to recognize when the final result of the addition is ready.
The testbench will apply all inputs (in_a, in_b, control, clk and reset_al) and verify the outputs, using assert statements to flag errors.
Verification process will apply inputs (in_a, in_b, control and reset_al) and verify the outputs, using assert statements to flag errors. A constant (an array of a record type) will be used to store the values for in_a, in_b, sum and carry. The values to be used for in_a and in_b are:
in_a
in_b
sum
carry
X”0”
X”4”
X”C”
X”E”
X”8”
X”A”
X”F”
X”F”
X”F”
X”1”
X”A”
X”5”
X”2”
‘0’
X”8”
X”7”
Please fill out the rest of the table and include it in your report (use ’hex’ notation). Do not change the result A+5 (see the 6th row of the above table). I know that it is wrong.
Your testbench checks the result and if any error occurs assert statement should give appropriate message. Timing is a crucial thing in your testbench. Remember to reset the circuit before you start a new addition. Explain why it is important.
Implementation details for a 4-bit serial adder entity
inputs:
outputs:
in_a 4 bits
in_b 4 bits
control 2 bits (s1, s0)
clk 1 bit (100ns period)
reset_al 1 bit (asynchronous active low)
Sum 4 bits
carry 1 bit
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity four_bit_adder is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
carry : out STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0)
);
end four_bit_adder;
architecture four_bit_adder_arc of four_bit_adder is
component fa is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end component ;
signal s : std_logic_vector (3 downto 0);
begin
a0 : fa port map (a(0),b(0),'0',sum(0),s(0));
a1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
a2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
a3 : fa port map (a(3),b(3),s(2),sum(3),s(3));
carry <= s(3);
end four_bit_adder_arc;