Consider the following open-loop opamp circuit. Assume the unity-gain output buf
ID: 2081756 • Letter: C
Question
Consider the following open-loop opamp circuit. Assume the unity-gain output buffer is ideal. Assume V_T = 25mV, beta = beta = 100, and V = V = 100V. You may make reasonable approximations in your calculations. a) Calculate omega_t of the opamp. b) Calculate SR of the opamp. c) Now connect the opamp in its closed-loop, unity-gain configuration. Determine the closed-loop transfer function, A (s). (You may assume that A(s) = omega_t/s). d) With the opamp still in its closed-loop, unity-gain configuration, if v (t) is an square wave of amplitude plusminus 1V and frequency 250 kHz, sketch and label the output voltage, v_o(t). e) Calculate A_0 and omega_H of the opamp.Explanation / Answer
Slew rate is the maximum voltage change per unit time in a node of a circuit, due to limited current sink or source. The SR of a circuit is limited by its slowest node, i.e., the one with the smallest Slew rate. Imagine a node in a circuit where the load is capacitive-dominant, i.e., the load is mostly made of a capacitance C (although there is always some very large parallel resistance R).
For simplicity let's assume the parallel resistance is infinite, so that all current I entering the load will flow to the capacitor and none to the resistance. Then, the rate of voltage change across the capacitor is defined by the well-known formula:
dV/dt=I/C
If the current being sourced to this load is limited (and in reality always is), say at Imax, the maximum voltage change per unit time is:
SR=max(dVdt)=ImaxC
This is the Slew-Rate. If the current is being drawn from the capacitor, i.e., the capacitor is discharging, the same rule applies, except the voltage change is negative (negative SR).
One common characteristic of an opamp is the Slew-Rate. It tells how fast the opamp can charge a capacitor at its ouput and its a measure of its driving power. That, of course, depends on the value of the capacitive load and its ability to provide current. SR in the circuit perspective has already been described above. Now we will look at the transistor level. If you are interested in this example and you need to review the necessary equations, read this topic.
Let's look at the two most ordinary stages of the opamp: the differential pair and the output stage. The analysis of Slew-Rate is a large-signal analysis, therefore we will consider large swings of the input signal. In particular, we will assume that the input differential voltage vd=v+v is high enough to let all internal nodes hit the rails (voltage supply for driving PMOS and ground for driving NMOS). It is common that the second stage has a compensation capacitor CC for stability purposes. If it does not have, think of CC as the parasitic capacitors of the PMOS transistor.