Please explain the function of this VHDL code and show how can it be written dif
ID: 2083892 • Letter: P
Question
Please explain the function of this VHDL code and show how can it be written differently.
This is a ZOOM IN/OUT code. Please add comments to understand the connection between the older code and the newer code.
library ieee;
use ieee.std_logic_1164.all;
-
entity key_pre is
generic(WITCH : integer := 1);
port(
clock : in std_logic;--ʱÖÓ
KEY : in std_logic_vector(WITCH-1 downto 0);--°´¼üÊäÈë
KEY_p : out std_logic_vector(WITCH-1 downto 0)--°´¼ü¼ì²âÂö³å
);
end key_pre;
architecture rtl of key_pre is
signal KEY_d : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal KEY_d1 : std_logic_vector(WITCH-1 downto 0):=(others=>'1');
signal KEY_d2 : std_logic_vector(WITCH-1 downto 0):=(others=>'1');
signal KEY_q1 : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal KEY_q2 : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal cnt_20ms : integer :=0;
signal clock_20ms : std_logic:='0';
begin
process(clock)
begin
if(clock'event and clock = '1') then
if(cnt_20ms<500000) then
cnt_20ms<=0;
clock_20ms<=not clock_20ms;
else
cnt_20ms<=cnt_20ms+1;
end if;
end if;
end process;
process(clock_20ms)
begin
if(clock_20ms'event and clock_20ms = '1') then
KEY_d1<=KEY;
KEY_d2<=KEY_d1;
KEY_d<=not(KEY_d1 or KEY_d2);
end if;
end process;
process(clock)
begin
if(clock'event and clock = '1') then
KEY_q1<=KEY_d;
KEY_q2<=KEY_q1;
KEY_p<=(KEY_q1 and (not KEY_q2));
end if;
end process;
end rtl;
Explanation / Answer
library ieee; -- Including ieee library
use ieee.std_logic_1164.all; -- Including std_logic_1164 package from ieee library
-
entity key_pre is -- Start of Entity key_pre
generic(WITCH : integer := 1); -- Generic WITCH declared
port(
clock : in std_logic; -- Input Clock of type std_logic
KEY : in std_logic_vector(WITCH-1 downto 0); -- Input KEY BUS of type std_logic_vector. Size of Bus is WITCH.
KEY_p : out std_logic_vector(WITCH-1 downto 0) -- Input KEY_p BUS of type std_logic_vector. Size of Bus is WITCH.
);
end key_pre; -- End of Entity
architecture rtl of key_pre is -- Start of Architecture rtl of Entity key_pre
-- Signals with std_logic_vector of width WITCH declared.
signal KEY_d : std_logic_vector(WITCH-1 downto 0):=(others=>'0'); -- All 0s
signal KEY_d1 : std_logic_vector(WITCH-1 downto 0):=(others=>'1'); -- All 1s
signal KEY_d2 : std_logic_vector(WITCH-1 downto 0):=(others=>'1'); -- All 1s
signal KEY_q1 : std_logic_vector(WITCH-1 downto 0):=(others=>'0'); -- All 0s
signal KEY_q2 : std_logic_vector(WITCH-1 downto 0):=(others=>'0'); -- All 0s
signal cnt_20ms : integer :=0; -- cnt_20ms signal of integer type
signal clock_20ms : std_logic:='0'; -- clock_20ms signal of std_logic type
begin
process(clock) -- Start of process with sensitive signal 'clock'
begin
if(clock'event and clock = '1') then -- If Positive edge of 'clock'
if(cnt_20ms > 500000) then -- This if condition is used for generation of 'clock_20ms' from 'clock'
cnt_20ms <= 0; -- The frequecy of clock_20ms = (clock / 2 x 500000)
clock_20ms <= not clock_20ms; -- i.e The 'clock_20ms' is togggle after 500000 positive edges of 'clock'
else
cnt_20ms <= cnt_20ms + 1;
end if;
end if;
end process;
process(clock_20ms) -- Start of process with sensitive signal 'clock_20ms'
begin
if(clock_20ms'event and clock_20ms = '1') then -- If Positive edge of 'clock_20ms'
KEY_d1 <= KEY; -- Copy of Input KEY Vector to Signal KEY_d1 Vector .
KEY_d2 <= KEY_d1; -- Copy of Signal KEY_d1 Vector to Signal KEY_d2 Vector
KEY_d <= not(KEY_d1 or KEY_d2); -- This will assign the inverse of Input KEY vector to KEY_d.
end if; -- i.e. KEY_d1 = KEY_d2 = Key_d So, KEY_d = not (KEY)
end process;
process(clock) -- Start of process with sensitive signal 'clock'
begin
if(clock'event and clock = '1') then
KEY_q1 <= KEY_d; -- Copy of Signal KEY_d Vector to Signal KEY_q1 Vector
KEY_q2 <= KEY_q1; -- Copy of Signal KEY_q1 Vector to Signal KEY_q2 Vector
KEY_p <= (KEY_q1 and (not KEY_q2)); -- KEY_p = 0b'0000_0000 i.e all the pins are zero.
end if;
end process;
end rtl;