In the class account I have included the user guide for the Xilinx MMCM. For you
ID: 2084285 • Letter: I
Question
In the class account I have included the user guide for the Xilinx MMCM. For your class project you will write VHDL code to implement a circuit that will create .5X, 2X, 3X and 4X clock signals. The input to your circuit is the signal CLK_IN_100, a 100 MHz clock signal. The output signals to your circuit are CLK_OUT 50, CLK_OUT_100, CLK_OUT_200, CLK_OUT_300, and CLK_OUT_400. These should be synchronized clock outputs with frequencies 50MHz, 100MHz, 200MHz, 300MHz, and 400MHz respectively. You will use the built in MMCM component to implement your clocks. To create the different output frequencies, you will set the proper generics (see your labs for examples) for the five different output clock signals.Explanation / Answer
By using this the best result would be CLKOUT50,CLKOUT100,CLKOUT200,CLKOUT300,CLKOUT400 of the MMCM and the route that directly to the BUFIO.this will use the hign performance clock signals.The BUFIO can the clock an ODDR to mirror the clock out.The MMCM,BUFIO,ODDR have in the same path.But setting the PACKAGE_PIN for the output pin should result in the tools choosing the correct region for the BUFIO and MMCM.However your frequencies 50MHZ,100MHZ,200MHZ has to be in a location that can reach the MMCM,So the 50MHZ & 100MHZ clock input and high speed clock output needs to be in the same clock signals.