Pipeline. For the following questions, consider a pipelined MIPS processor with
ID: 2247256 • Letter: P
Question
Pipeline. For the following questions, consider a pipelined MIPS processor with the following stages and stage delays. IF = 38ns ID = 20ns EX = 33ns Mem = 55ns WB = 22ns (a) What is the cycle time for this processor? (b) How long would the cycle time be for a single cycle version of this processor (stage delays remain the same) (c) Assuming that there is an average of 1 NOP for every 13 instructions to handle hazards, what is the speedup of this processor in relation to its single cycle counterpart?Explanation / Answer
Answer:
For pipeline , clock cycle time = max{stage delay}
= max {38,20,33,55,22}
= 55ns
Fo non pipeline , clock cycle time = sum of delays in each statge = 38+20+33+55+22 = 168ns
speedup (no of instructions not givent) = time for non pipeline/time pipeline
=168/55
=3.05