Please double check your work. Thank you. 3. Suppose the logic blocks in a proce
ID: 2248065 • Letter: P
Question
Please double check your work. Thank you.
3. Suppose the logic blocks in a processor have the following latencies.. Data access Register write 350ps 150ps 175ps 500ps 200ps a) In a single cycle, non-pipelined processor, what is the minimum time between instructions for an application executing only R-type instructions? b) In a single cycle, non-pipelined processor, what is the minimum time between instructions for an application executing R, I, and J-type instructions? c) If the logic blocks above are each implemented as individual pipeline stages, what would be the minimum time between instructions for this pipelined CPU if hazards are ignored?Explanation / Answer
a) R type instructions are completed in 4th step ( i.e, Data Access) so 5 th step Register write step is not required for R-type instructions. So, application executing R type instruction need 4 steps only.
So, minimum time between instructions = Instruction fetch latency + Register read atency + ALU operation latency + Data access latency
= 350ps + 150ps + 175ps + 500 ps
= 1175 ps
b) Application executing R, I and J type instruction needs all 5 steps.
So, minimum time between instructions = Instruction fetch latency + Register read atency + ALU operation latency + Data access latency + Register write latency
= 350ps + 150ps + 175ps + 500 ps +200 ps
= 1375 ps
c) Pipelining reduces the cycle time to longest stage latency. Here the longest stage/ step is Data access which has latency.
so minimum time between instructions for this pipeline CPU if hazards are ignored is latency of Data access i.e, 500ps .