I will really appreicate the help. Thanks! These are bonus questions that I am a
ID: 2249195 • Letter: I
Question
I will really appreicate the help. Thanks! These are bonus questions that I am allowed to put on a cheat sheet.
27.What is a control hazard in the MIPS pipeline? 28.How can a forwarding unit prevent both data and control hazards? 29.Why does the forwarding unit not always work? 30.How is this problem overcome by stalling? 31.What is the latencv in a hard disk drive? 32.True or false: Cache memorystatic RM, is composed of flip-flops Dynamic random access memory (or DRAM) is a much simpler electronic memory with only one transistor per cell.Explanation / Answer
27.Control hazards in mips occurs when we donot know which instruction has to be executed next.They result from the pipelining of branches and other instructions which change the PC.Normally we see that PC has to be incremented by one after each instruction fetch .But for branch instruction it is different.If the branch instruction is executed and if the condition is true than the branch is taken and new address for fetching the next instruction has to be calculated and stored in PC.This new address will not be known til the EX stage .At the same time, several new instructions following the branch instructions might have entered the pipeline. They also might have been partially executed. They must be removed from the pipeline and operations must be undone.Such an effect is known as control hazard
28.The forwarding unit elimanates the hazards by detecting the dependencies and forwards the required data from the instruction which is running the data to the instruction that requires the data.Hence stalling is not required