Partl a basic Moore FSM Circuit description We will design a game on a 7-segment
ID: 2250017 • Letter: P
Question
Partl a basic Moore FSM Circuit description We will design a game on a 7-segment display (SSD). The diagram is shown in Fig.I clk 1 CLOCK,50 fsm1 --| clock KEY[0] Fig.1 The diagram of a SSD game. The first module clock generates a 1 Hz clock signal, clk 1, from a 50MHz clock signal, CLOCK 50. With clk_1 as clock input and KEY[0] as reset, module fsm1 delivers HEXO[0:6] to drive a 7-segment display on DE2 board The LEDs in the 7-seg display are turned on according to the following sequence a ab b bc09cd-Pddeeefaa( repeat ). It looks like the light moves around in a clockwise direction. Sometimes a single LED is turned on, and sometimes two LEDs are turned on. In either case, LED(s) is on for 1 second.Explanation / Answer
//clock divider
module clockdivider (CLOCK_50, clk_1);
input CLOCK_50;
output clk_1;
reg [25:0] counter =26’d0;
parameter divisor = 26’d50000000 // Divide 50 MHz with 50000000 to get 1 Hz clock
always @(posedge CLOCK_50)
begin
counter <= counter + 26’d1;
if (counter >= (divisor – 1))
counter <= 26’d0;
end
assign clk_1 = (counter < divisor/2) ? 1’b0 : 1’b1;
end module
//FSM Module
module fsm1 (clk, rst, HEX0);
input clk;
input rst;
output reg [6:0] HEX0;
reg [3:0] state;
always @ (posedge clk)
begin
if (!rst)
state <= 4’b0000;
else
case (state)
4’b0000: //a
begin
state <= 4’b0001;
HEX0 <= 7’b0111111;
End
4’b0001: //ab
begin
state <= 4’b0010;
HEX0 <= 7’b0011111;
end
4’b0010: //b
begin
state <= 4’b0011;
HEX0 <= 7’b1011111;
end
4’b0011: //bc
begin
state <= 4’b0100;
HEX0 <= 7’b1001111;
end
4’b0100: //c
begin
state <= 4’b0101;
HEX0 <= 7’b1101111;
end
4’b0101: //cd
begin
state <= 4’b0110;
HEX0 <= 7’b1100111;
end
4’b0110: //d
begin
state <= 4’b0111;
HEX0 <= 7’b1110111;
end
4’b0111: //de
begin
state <= 4’b1000;
HEX0 <= 7’b1110011;
end
4’b1000: //e
begin
state <= 4’b1001;
HEX0 <= 7’b1111011;
end
4’b1001: //ef
begin
state <= 4’b1010;
HEX0 <= 7’b1111001;
end
4’b1010: //f
begin
state <= 4’b1011;
HEX0 <= 7’b1111101;
end
4’b1011: //fa
begin
state <= 4’b0000;
HEX0 <= 7’b0111101;
end
end case
end
end
endmodule
//TOP MODULE
module lab5_part1 (CLOCK_50, KEY, HEX0);
input CLOCK_50;
input KEY;
output reg [6:0] HEX0;
wire clk;
//instantiate sub modules
clockdivider (CLOCK_50, clk);
fsm1 (clk, KEY, HEX0);
endmodule