Consider the following three pipeline processor implementations. Assume that all

Question

Consider the following three pipeline processor implementations. Assume that all 3 pipelines can achieve a CPI of 1, except for mispredicted branches.

Implementation X: A pipeline length of 20 stages with branches resolving in stage 7, running at 666MHz.

Implementation Y: A pipeline length of 30 stages with branches resolving in stage 12, running at 1GHz.

Implementation Z: A pipeline length of 25 stages with branches resolving in stage 5, running at 833MHz.

For all processors, the branch predictor is located in stage 1. What are the cycle times for each of these pipelines, in nanoseconds?

Explanation / Answer

CPI = 1

Implentation of X:

T = I * CPI * C

   = 666 * 1 * 13

   = 8658MHz

Implementation of Y:

T = I * CPI * C

   = 1000 * 1 * 18

   = 18000MHz

Implementation of z:

T = I * CPI * C

   = 833 * 1 * 20

   = 16660 MHz

When branch predictor is located in stage 1, the cycle times for each of these pipelines in nanoseconds = 0.13664 ns

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