Register File The register file contains eight register modules and follows a tw
ID: 2268347 • Letter: R
Question
Register File The register file contains eight register modules and follows a two-read, one-write format. See Figure 2 Inputs (One bit unless noted otherwise): -rd1, rd2 (3 bits): Readl and read2. Selects which registers to read from -wr (3 bits): Write. Selects which register to write to. them to address all eight Note that the previous signals are 3 bits long, allo registers -in (16 bits): Data to be written to the appropriate register clk: Clock signal we: Write enable. Enabling allows register contents to be written - rst: Resets all registers. Asynchronous. Outputs: - out1, out2 16 bits): Parallel outputs containing the data from the selected registers, Hints e Use the output of the 3-to-8 decoder in conjunction with the register file's we signal to e Use two 8-to-1 MUXs, one to connect the output of the register specified by rdl to .Do not use parameters in the entity of the register file, however, generics should still drive the e on the register module. out1, and a second for rd2 and out2, be used when instantiating the various components. (Note: The reason for this is that the generic would then have to be set in a higher level, of which there are none.) we out1 rst Reg. File clk out2 Figure 2: Register FileExplanation / Answer
-- This is the AND gate
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port( A, B, C : in std_logic;
F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B and C;
end func;
--*============================
-- This is the NOT gate
library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
--
architecture func of notGate is
begin
outPort <= not inPort;
end func;
--*=======================*======================
-- Now we write the definition for the 3-to-8 Decoder
library ieee;
use ieee.std_logic_1164.all;
--
entity Decoder_3to8 is
port( A0, A1, A2 : in std_logic;
D0, D1, D2, D3, D4, D5, D6, D7 : out std_logic);
end Decoder_3to8;
--
architecture func of Decoder_3to8 is
component andGate is --import AND Gate entity
port( A, B, C : in std_logic;
F : out std_logic);
end component;
component notGate is --import NOT Gate entity
port( inPort : in std_logic;
outPort : out std_logic);
end component;
signal invA0, invA1, invA2 : std_logic;
begin
--notice that there are as many concurrent statements
--here as there are gates in the physical circuit shown
-- on Teahlab.com.
GI1: notGate port map(A0, invA0);
GI2: notGate port map(A1, invA1);
GI3: notGate port map(A2, invA2);
--the outputs
GA1: andGate port map(invA0, invA1, invA2, D0);
GA2: andGate port map( A0, invA1, invA2, D1);
GA3: andGate port map(invA0, A1, invA2, D2);
GA4: andGate port map( A0, A1, invA2, D3);
GA5: andGate port map(invA0, invA1, A2, D4);
GA6: andGate port map( A0, invA1, A2, D5);
GA7: andGate port map(invA0, A1, A2, D6);
GA8: andGate port map( A0, A1, A2, D7);
end func;
---------------------------------------------------------END
---------------------------------------------------------END
Test Bench:
---import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--declare entity: no inputs, no outputs
entity Decoder_3to8_tb is
end Decoder_3to8_tb;
-- Describe how to test the Three-Eight-Decoder
architecture tb of Decoder_3to8_tb is
--pass Decoder_3to8 entity to the testbench as component
component Decoder_3to8 is
port( A0, A1, A2 : in std_logic;
D0, D1, D2, D3, D4, D5, D6, D7 : out std_logic);
end component;
signal A0, A1, A2, D0, D1, D2,
D3, D4, D5, D6, D7 : std_logic;
begin
-- map the testbench signals to the ports
-- of the Decoder_3to8
mapping: Decoder_3to8
port map(A0, A1, A2, D0, D1, D2, D3, D4, D5, D6, D7);
process
variable errCnt : integer := 0;--variable to track errors
begin
--TEST 0
A0 <= '1';
A1 <= '0';
A2 <= '1';
wait for 15 ns;
assert(D0 = '0') report "Error 0" severity error;
assert(D1 = '0') report "Error 0" severity error;
assert(D2 = '0') report "Error 0" severity error;
assert(D3 = '0') report "Error 0" severity error;
assert(D4 = '0') report "Error 0" severity error;
assert(D5 = '1') report "Error 0" severity error;
assert(D6 = '0') report "Error 0" severity error;
assert(D7 = '0') report "Error 0" severity error;
if(D0 /= '0' or D1 /= '0' or D2 /= '0' or D3 /= '0' or
D4 /= '0' or D5 /= '1' or D6 /= '0' or D7 /= '0') then
errCnt := errCnt + 1;
end if;
--TEST 1
A0 <= '1';
A1 <= '1';
A2 <= '1';
wait for 15 ns;
assert(D0 = '0') report "Error 1" severity error;
assert(D1 = '0') report "Error 1" severity error;
assert(D2 = '0') report "Error 1" severity error;
assert(D3 = '0') report "Error 1" severity error;
assert(D4 = '0') report "Error 1" severity error;
assert(D5 = '0') report "Error 1" severity error;
assert(D6 = '0') report "Error 1" severity error;
assert(D7 = '1') report "Error 1" severity error;
if(D0 /= '0' or D1 /= '0' or D2 /= '0' or D3 /= '0' or
D4 /= '0' or D5 /= '0' or D6 /= '0' or D7 /= '1') then
errCnt := errCnt + 1;
end if;
--TEST 2
A0 <= '1';
A1 <= '1';
A2 <= '0';
wait for 15 ns;
assert(D0 = '0') report "Error 2" severity error;
assert(D1 = '0') report "Error 2" severity error;
assert(D2 = '0') report "Error 2" severity error;
assert(D3 = '1') report "Error 2" severity error;
assert(D4 = '0') report "Error 2" severity error;
assert(D5 = '0') report "Error 2" severity error;
assert(D6 = '0') report "Error 2" severity error;
assert(D7 = '0') report "Error 2" severity error;
if(D0 /= '0' or D1 /= '0' or D2 /= '0' or D3 /= '1' or
D4 /= '0' or D5 /= '0' or D6 /= '0' or D7 /= '0') then
errCnt := errCnt + 1;
end if;
--TEST 3
A0 <= '0';
A1 <= '1';
A2 <= '0';
wait for 15 ns;
assert(D0 = '0') report "Error 3" severity error;
assert(D1 = '0') report "Error 3" severity error;
assert(D2 = '1') report "Error 3" severity error;
assert(D3 = '0') report "Error 3" severity error;
assert(D4 = '0') report "Error 3" severity error;
assert(D5 = '0') report "Error 3" severity error;
assert(D6 = '0') report "Error 3" severity error;
assert(D7 = '0') report "Error 3" severity error;
if(D0 /= '0' or D1 /= '0' or D2 /= '1' or D3 /= '0' or
D4 /= '0' or D5 /= '0' or D6 /= '0' or D7 /= '0') then
errCnt := errCnt + 1;
end if;
-------------- SUMMARY -------------
if(errCnt = 0) then
assert false report "Good!" severity note;
else
assert false report "Error!" severity error;
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of Decoder_3to8_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX8_1 IS
PORT ( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A,B,C,D,E,F,G,H :IN STD_LOGIC;
MUX_OUT: OUT STD_LOGIC );
END MUX8_1;
ARCHITECTURE BEHAVIORAL OF MUX8_1 IS
BEGIN
PROCESS (SEL,A,B,C,D,E,F,G,H)
BEGIN
CASE SEL IS
WHEN "000" => MUX_OUT <= A;
WHEN "001" => MUX_OUT <= B;
WHEN "010" => MUX_OUT <= C;
WHEN "011" => MUX_OUT <= D;
WHEN "100" => MUX_OUT <= E;
WHEN "101" => MUX_OUT <= F;
WHEN "110" => MUX_OUT <= G;
WHEN "111" => MUX_OUT <= H;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END BEHAVIORAL;