The following statement ARM machine code is represented in machine code as the f
ID: 2291079 • Letter: T
Question
The following statement ARM machine code is represented in machine code as the following AND R2, R2, 0xFFFFFFFD ARM statement and its machine code: 00001008 : E3C22002 AND R1, R1, 0xFFFFFFFD Questions: 1. Is the above statement is valid ARM instruction? [1] 2. For the both answers in 1 (valid or non-valid), explain why? [1] 3. Is this a pseudo-instruction? [1] 4. Justify (The Data processing instruction format is shown below. [1] 31 28 25 20 16 15 12 11 0 SI Rn Rd and 2 Operation Code 0000-AND 0001-EOR 0010 # SUB 0011-RSB 0100 ADD 1000 TST 1100-ORR 01 01=ADC 1001.TEQ 1101-MOV 0110 SBC 1010 CMP 1110 BIC 0111 RSC 1011 CMN 1111 MVNExplanation / Answer
Answer :- 1) No, the instruction is not a valid ARM instruction.
Answer :- 2) The actual syntax for AND is-
AND Rd, Rn, N. Where N is 12-bit immediate operand. Here the given instruction is not following the same pattern. Hence the statement is not a valid one.
Answer :- 3) No, this is not a pseudo-instruction.
Answer :- 4) The instruction format contains all the information such as-
Condition :- The MSB 4-bits are used to indicate the conditional execution of the instruction.
I :- This bit if zero then operand2 is a register otherwise operand2 is a 12-bit immediate value.
Opcode :- Opcode field tells about the actual instruction. 4-bits are assigned for this purpose.
S :- This bit used to check whether flags bits would be affected from this instruction or not.
Rn :- The source register number
Rd :- The destination register number
Operand2:- This is the second source operand