Design Task 2: One Second Prescalar In many systems it is desirable to have a ve
ID: 2291462 • Letter: D
Question
Design Task 2: One Second Prescalar In many systems it is desirable to have a very fast system clock to clock most of the sequential entities in the system. However, there may be other sequential entities in the same system that need to be clocked at a much slower speed. An approach that allows flexibility in generating a slower clock frequency is a frequency divider, also called a prescalar. This is basically a counter that generates a pulse every n cycles of its input clock. The output occurs as a pulse with a frequency that is 1/n of the input clock frequency. However, the output pulse has a fixed duration that is one clk period long. 4 The prescalar to be designed is named one_sec_prescalar. If its cnt_en input is asserted at a rate of 32.768 kHz it must generate an output pulse every second. So, this design divides down it input by 32768. The input pulse is one system clock in duration and output pulse is one system clock in duration. This entity must also generate an output named one_hz that is a 1Hz square wave. The entity declaration for the one second prescalar is:
entity one_sec_prescalar is port( clk : in std_logic; -- system clock
rst_n : in std_logic; -- active low synchronous reset
clr_n : in std_logic; -- synchronous clear
cnt_en : in std_logic; -- count enable
one_hz : out std_logic; -- one Hz square wave output
one_sec_tick : out std_logic -- one clock wide pulse every sec );