Please give a good explanation about your answer, do not answer it if you do not
ID: 2291896 • Letter: P
Question
Please give a good explanation about your answer, do not answer it if you do not know it!
6. (7%) All necessary information on the 74LS163 counter is given on the next page The circuit consists of two 74x163 counters, wired up as shown. The outputs are Q7, Q6, ..., Qo 74x163 74x1G3 CLK dCLA Clk LD ENP OENT NRCO ENP ENT 13 ?? 01 C Q Q3 15 RCO NRCO The circuit: Multiple choice answers: a) Counts infinitely from (0)d to (255)d b) Counts infinitely from (16), to (255)d c) Counts infinitely from (4), to (255)c d) Counts one round from (0) to (255)d and stops e) Counts one round from (16) to (255)d and stops f) Counts one round from (4)d to (255) and stops g) None of the answers above is correct. 8Explanation / Answer
IC 74x163 is a synchronous 4 bit counter, and here in the question two such ICs are cascaded together to count between (00000000)2 / 010 to (11111111)2 / 25510.
RCO is a ripple Carry output which is asserted high when count value of (1111)2 is reached in a 74x163 IC.
CLR (Clear) and LD ( Load) are active low signals and CLR can asynchronously clear the output to 0000 if asserted LOW and LD will synchronously load a new value to the counter provided by ABCD if asserted LOW.
Here in the circuit , CLR is tied to 1 to avoid any unintentional trigger.
ENP and ENT are count enable signals tied to logic 1 at first stage and RCO output of first stage drives ENP/ENT of second stage.
Ripple Carry Out (RCO) becomes logic '1' when count of first stage IC reaches 1111 and hence next stage IC (Higher nibble) increments its count by 1, meanwhile in next clock first stage IC restarts count from 0000 whereas RCO again becomes LOW.
Hence after every 0000-1111 count of 1 stage , the 2nd stage count is incremented by 1.
Hence in effect it works as a 8 - bit counter.
When 2nd stage output reaches 1111 it means 8 bit counter have reach its highest count value of 11111111 and RCO pin of 2nd stage is inverted (NRCO) to make it logic 0 which in turn asserts the load , LD signal of first stage counter and ABCD=0000 is loaded to first count and again counter continues its up counting.
Hence correct answer of the question is (a) Counts infinitely between 010 - 25510