Part 1. Write a Verilog code file that synthesizes to a state machine for the tr
ID: 2293514 • Letter: P
Question
Part 1. Write a Verilog code file that synthesizes to a state machine for the traffic controller. The design should consist of (at least) two always block. The first always block, should implement the output forming logic for the Moore state machine.
Part 2. Write a Verilog file that synthesizes to a state machine for the sequence detector. The design will consist of at least two always blocks. The first always block, will implement the clocked design. The second always blocks will implement the finite state machine logic for the Mealy State machine.
Part 1: Design Traffic Light Controller In part 1 of the lab, you will design and implement a Moore state machine for a traffic light controller with the following description/specifications A little used farm road intersects with a multi-lane highway; a traffic light controls the traffic at the intersection. Detectors are placed along the little used farm road which causes the signal implemented to maximize the time the highway light remains green. O00 For maintenance purposes, a synchronous signal "RESET forces all lights in all directions to be red for a 2 second time period after the RESET signal is '0'. After this RESET, normal operation of the traffic signal system will resume. There is a SENSOR on the farm road to determine when a vehicle is present. When the SENSOR indicates that there is a farm road vehicle present, the highway light turns yellow for 4 seconds before turning red. Simultaneously, the farm road signal turns green for 6 seconds, (allowing the farm road vehicle to enter the highway), and then yellow for 4 seconds before returning to red, (with the highway light simultaneously returning to green. At this point, the system is only allowing highway traffic to flow.Explanation / Answer
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module sequence_detector(sequence,overlap,detect,clk,q);
input [15:0]sequence;
reg [15:0]temp;
reg bitin;
input overlap;
input [4:0]detect;
input clk;
output reg q;
integer i=0;
reg [2:0]pstate;
parameter A = 3'b000, B = 3'b001, C = 3'b011, D = 3'b100, E = 3'b101;
initial begin
pstate <=A;
$monitor("Pstate=%d bit=%b q=%b",pstate,bitin,q);
end
always @(posedge clk)begin
if(i==0)
temp = sequence;
i = i + 1;
end
always @(posedge clk)begin
bitin = temp[15];
temp=temp<<1;
if(overlap==1'b1)begin
case(pstate)
A:
if(bitin==1'b1)begin
pstate = B;
q = 0;
end
else begin
pstate = A;
q = 0;
end
B:
if(bitin==1'b1)begin
pstate = C;
q = 0;
end
else begin
pstate = A;
q = 0;
end
C:
if(bitin==1'b0)begin
pstate = D;
q = 0;
end
else begin
pstate = C;
q = 0;
end
D:
if(bitin==1'b1)begin
pstate = E;
q = 0;
end
else begin
pstate = A;
q = 0;
end
E:
if(bitin==1'b1)begin
pstate = C;
q = 1;
end
else begin
pstate = A;
q = 0;
end
endcase
end
else if(overlap==1'b0) begin
case(pstate)
A:
if(bitin==1'b1)begin
pstate = B;
q = 0;
end
else begin
pstate = A;
q = 0;
end
B:
if(bitin==1'b1)begin
pstate = C;
q = 0;
end
else begin
pstate = A;
q = 0;
end
C:
if(bitin==1'b0)begin
pstate = D;
q = 0;
end
else begin
pstate = A;
q = 0;
end
D:
if(bitin==1'b1)begin
pstate = E;
q = 0;
end
else begin
pstate = A;
q = 0;
end
E:
if(bitin==1'b1)begin
pstate = A;
q = 1;
end
else begin
pstate = A;
q = 0;
end
endcase
end
end
endmodule