Could anyone help me this project? I need vhdl code and testbench code. In this
ID: 2989395 • Letter: C
Question
Could anyone help me this project?
I need vhdl code and testbench code.
In this lab, you will design a digital lock. The lock will have four buttons for you to enter a secret three-digit code to unlock it. You will use the pushbuttons BTN (3:0) 011 the FPGA board for this -BTN (O) will represent the digit 'O'. BTN (l) the digit '1', BTN(2) the digit '2'. and BTN(3) the digit '3'. The secret code is 3-1-0. So you must press '3'. followed by '1', and then 'O' in order to open the lock. If you entered the correct code. LED LDO will light up to indicate that the lock is open. If the code is incorrect. LD7 will light up instead. You must make three button pressings before you know if you have entered the correct code or not. While you are keying in the code, all LEDs will be off. The following is the top-level schematic of the digital lock. It consists of 2 modules - the lock module and the pushbutton debouncing module. The 'C'LR' input is active low and is mapped to a slide switch. The 'clock' is to be connected to the onboard 50Mhz FPGA clock at location B8. Z (0) is mapped to LDO to indicate a correct code while z (l) is mapped to LD7 to indicate an incorrect code. Figure 1 You need to design the state machine for the lock module. A sample state diagram is provided 011 the next page for a simple lock that accepts a two-digit secret code of 0-1. You can use it as a reference and modify it for your design. After this, write the behavioral VHDL code for the lock module. You can test your design by simulating it using a test bench. A sample test bench is also provided 011 the next page. You need to modify it to test for the correct secret code as well as an incorrect code. In your simulation, you need to display the state in the waveforms so that you can check it. The code for the debouncing module is provided 011 the next page: you can use it as is. hi the previous lab. you must have seen the undesirable effect of a bouncing switch. Basically, when you press a pushbutton, instead of going from 0 to 1 cleanly, it may bounce back and forth between 0 and 1 for a few milliseconds. So a debouncing circuit is needed to prevent any errors in the circuit operations. Once the modules are completed, write the structural VHDL code for the top-level design by instantiating the lock module and the debouncing module using the component/port map statements. After this, implement the design and transfer it to the FPGA board. You will need to create a new implementation constraints file to map the signals to the pushbuttons. LEDs, slide switch, and onboard 50Mhz clock.Explanation / Answer
VHDL CODE FOR DIGITAL CLOCK
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity digi_clk is
port (clk1 : in std_logic;
seconds : out std_logic_vector(5 downto 0);
minutes : out std_logic_vector(5 downto 0);
hours : out std_logic_vector(4 downto 0)
);
end digi_clk;
architecture Behavioral of digi_clk is
signal sec,min,hour : integer range 0 to 60 :=0;
signal count : integer :=1;
signal clk : std_logic :='0';
begin
seconds <= conv_std_logic_vector(sec,6);
minutes <= conv_std_logic_vector(min,6);
hours <= conv_std_logic_vector(hour,5);
--clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;
process(clk) --period of clk is 1 second.
begin
if(clk'event and clk='1') then
sec <= sec+ 1;
if(sec = 59) then
sec<=0;
min <= min + 1;
if(min = 59) then
hour <= hour + 1;
min <= 0;
if(hour = 23) then
hour <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
TESTBENCH CODE
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
PORT(
clk : IN std_logic;
count : OUT std_logic_vector(3 downto 0);
reset : IN std_logic
);
END COMPONENT;
--declare inputs and initialize them
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--declare outputs and initialize them
signal count : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
clk => clk,
count => count,
reset => reset
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
-- Stimulus process
stim_proc: process
begin
wait for 7 ns;
reset <='1';
wait for 3 ns;
reset <='0';
wait for 17 ns;
reset <= '1';
wait for 1 ns;
reset <= '0';
wait;
end process;
END;