Design a 4-to-2 priority encoder with an enable input, using gates. (See Unit 9,

ID: 2990269 • Letter: D

Question

Study Guide Part 4(b)).When enable is 0, all outputs are 0. Write a VHDL module

for the encoder. Use the following port declaration:

Port ( y : in std_logic_vector(0 to 3);

enable : in std_logic; a1,b1,c1 : out std_logic);

(b) Design an 8-to-3 priority encoder (Figure 9-16) with an enable input, using two

of the 4-to-2 priority encoders you designed in (a), three OR gates, an AND

gate, and one inverter. Then write a VHDL module for this encoder. Use the

port declaration:

Port ( y : in std_logic_vector(0 to 7);

main_enable : in std_logic; a,b,c,d : out std_logic);

(Hint : In building the 8-to-3 encoder, use one 4-to-2 encoder for the four most

significant bits, and another for the four least significant bits.Also, outputs b and

c of the 8-to-3 encoder should come from OR gates. The enable input to the

encoder for the least significant bits depends on the main_enable signal and the

c1 output from the encoder for the most significant bits.)

4-2 priority encoder