The code given as several flaws. Hint: With the way, this VHDL code is written,
ID: 3349677 • Letter: T
Question
The code given as several flaws.
Hint: With the way, this VHDL code is written, when would state change? Are there typos?
Find these and create a corrected VHDL moldule.
- Moore model FSM (see Fig. 19) entity Moore_Model_Fig_ 5_19_vhdl is port (y out: out, bit_ vector 1 downto 0; x in, clock, reset: in bit); end Moore_Model_vhdl; architecture Behavioral of Moore_ Model_Fig_5_19 is type State_type is (SO, S1, S2, S3); signal state: State_type process (Clk, reset) begin - names of states - State transition if rst = O' state if not x-in => if x-in then stateExplanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Moore_Model_Fig_5_19 is
port (
y_out : out bit_vector (1 downto 0);
x_in : in bit;
clock : in bit;
reset : in bit
);
end Moore_Model_Fig_5_19;
architecture Behavioral of Moore_Model_Fig_5_19 is
type State_type is (S0, S1, S2, S3);
signal state : State_type;
begin
Process1: process (clock,reset) -- Current State Logic
begin
if (reset = '0') then
state <= S0;
elsif (clock'event and clock = '1') then
case (state) is
when S0 =>
if (x_in = '0') then
state <= S1;
else
state <= S0;
end if;
when S1 =>
if (x_in = '0') then
state <= S2;
else
state <= S3;
end if;
when S2 =>
if (x_in = '0') then
state <= S3;
else
state <= S2;
end if;
when S3 =>
if (x_in = '0') then
state <= S0;
else
state <= S3;
end if;
end case;
end if;
end process Process1;
y_out <= "00" when state = S0 else
"01" when state = S1 else
"10" when state = S2 else
"11";
end Behavioral;