I\'m trying to get a 4 bit adder to run in VHDL. I keep getting errors but not s
ID: 3549722 • Letter: I
Question
I'm trying to get a 4 bit adder to run in VHDL. I keep getting errors but not sure what I'm doing wrong. Please advise! Thank you..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity alu is
port( AI: in std_logic_vector(3 downto 0);
BI: in std_logic_vector(3 downto 0);
SEL: in BIT;
SO: out std_logic_vector(4 downto 0));
end alu;
architecture behv of alu is
begin
process(AI,BI,SEL)
begin
case SEL is
when '0' => -- Error here "Bit type does not match integer literal."
SO <= AI + BI;
when '1' => -- Error here "Bit type does not match integer literal."
SO <= AI - BI;
end case;
end process;
end behv;
Explanation / Answer
The following file shows a portion of the VHDL description of the full adder component. This is the simplest model of the full adder. -- FA.vhd : full adder component library ieee; use ieee.std_logic_1164.all; entity FA is port(a, b : in std_logic; cin : in std_logic; cout : out std_logic; sum : out std_logic); end entity FA; architecture df_FA of FA is begin cout <= ???; sum <= a xor b xor cin ; end architecture df_FA;The following file shows a portion of the VHDL description of the structural model of the 4 - bit RCA, using four of the full adder components, shown in the previous VHDL file. -- file RCA.vhd library ieee; use ieee.std_logic_1164.all; entity RCA is port(a, b : in std_logic_vector(3 downto 0); cout : out std_logic; sum : out std_logic_vector(3 downto 0)); end entity RCA; architecture struct_RCA of RCA is signal cin: std_logic_vector(3 downto 0); component FA is port(a, b : in std_logic; cin : in std_logic; cout : out std_logic; sum : out std_logic); end component; begin cin(0) <= The following file shows a portion of the VHDL description of the structural model of the 4 - bit RCA, using four of the full adder components, shown in the previous VHDL file. -- file RCA.vhd library ieee; use ieee.std_logic_1164.all; entity RCA is port(a, b : in std_logic_vector(3 downto 0); cout : out std_logic; sum : out std_logic_vector(3 downto 0)); end entity RCA; architecture struct_RCA of RCA is signal cin: std_logic_vector(3 downto 0); component FA is port(a, b : in std_logic; cin : in std_logic; cout : out std_logic; sum : out std_logic); end component; begin cin(0) <=