Please help with the following question! It is about virtual memory. Consider th
ID: 3577014 • Letter: P
Question
Please help with the following question! It is about virtual memory.
Consider the 6-stage MIPS pipelined datapath on the opposite page. The PC register stores only the virtual-PC PC_v of the next instruction. What is the minimum possible clock-cycle time for this datapath? Explain your answer. On the above 6-stage pipeline, how many cycles are lost due to stalls/flushes for unconditional branches (j instructions) and conditional branches correctly predicted taken? Draw pipeline diagrams to explain your answer. Consider a new MIPS instruction jv imm($rs) that unconditionally jumps to the instruction at the virtual address stored at Mem[$rs + imm] (i.e.. jw imm($rs) is equivalent to 1w $reg, imm($rs); jr $reg). How many cycles are lost due to stalls/flushes for the jw instruction?Explanation / Answer
(a) The minimum clock-cycle time is the latency of the longest stage is,
read PCv then in parallel:
use TLB to get PCp; update PCv
(b) 2 cycles because the IT stage of the target instruction can only begin after the j instruction has computed the virtual branch target, which happens at the end of the ID stage. Hence, the IT stage of the target starts in cycle 4 instead of cycle 2 as shown below, a loss of two cycles:
1 2 3 4 5 6
j target IT IF ID* EX MM WB
target x x *IT IF ...
Stage Latency Explanation IT 10+max(100,0+10)read PCv then in parallel:
use TLB to get PCp; update PCv
IF 150 read instruction cache ID max(180+10,0,0+10) in parallel: read register file and possibly update PCv; possibly update PCv to target PCv EX 75+ max(100,0, 10) use ALU then do one of: translate address with TLB; possibly update PCv MM 180 read/write from/to data cache WB 180 update register file