Consider an out-of-order superscalar processor with 8 execution units. For the i

Question

Consider an out-of-order superscalar processor with 8 execution units. For the instructions given below, find the execution time with and without register renaming if any execution unit can execute any instruction and the latency of all instructions is 1 cycle. Assume the hardware register file contains enough registers to remap each destination register to a different hardware register and the pipeline depth = 5 stages.

LD r7, (r8)
MUL r1, r7, r2
SUB r7, r4, r5
ADD r9, r7, r8
LD r8, (r12)
DIV r10, r8, r10

Explanation / Answer

              LD hw7, (hw8)

             MUL hw1, hw7, hw2

              SUB hw17, hw4, hw5

            ADD hw9, hw17, hw8

             LD hw18, (hw 12)

             DIV hw10, hw18, hw10

With the register renaming, the program has been broken into three sets of two dependent instructions (LD and MUL, SUB and ADD, LD and DIV). The SUB and the second LD instruction can issue in the same cycle as the first LD. The MUL, ADD, and DIV instructions all issue in the next cycle, for a total execution time of 6 cycles.

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