I\'m trying to implement a verilog program and I\'m currently passing all but 25
ID: 3670716 • Letter: I
Question
I'm trying to implement a verilog program and I'm currently passing all but 252 cases from a total of 1440. My question is, how can I impove my code to allow all the test cases to pass. Thanks in advance!! Please just copy and paste my code as its rather long (testbench) and then from there, you'll be able to view which ones are giving me trouble from the logs.
Instructions for assignment:
Build a Verilog module named “calculator” that takes in two signed 16-bit numbers named “in1” and “in2” and performs the following functions depending on the value of another 4-bit input named “opCode”. Be aware that the opCode is not signed, like the inputs A and B of project 2. The outputs of the module “calculator” must be a signed 16-bit number named “result”, and a 1-bit “overflow”. Be aware that the value of “overflow” doesn’t always get calculated the same way, it depends on the operation. The value of the output “overflow” will be one if an overflow occurred or the value of “result” is not completely accurate or correct; else the output “overflow” will be zero.
My verilog code:
module Calculator(in1,in2,opCode,result,overflow);
input signed[15:0] in1, in2;
input[3:0] opCode;
output reg signed[15:0] result;
output reg overflow;
always @ (*) begin
if(opCode == 0000) begin
if(in1+in2<=32767 & in1+in2>= -32768) begin
overflow = 0;
end
else
begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0001) begin
if(in1-in2<=32767 & in1-in2>= -32768) begin
overflow = 0;
end
else
begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0010) begin
if(in1*5<=32767 & in1*5>= -32768) begin
overflow = 0;
end
else
begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0011) begin
if ((in1 % 10) == 0) begin
overflow = 0;
end else begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0100) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 0101) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 0110) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 0111) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 1000) begin
if(in1 == 32767) begin
overflow = 1;
end
else begin
overflow = 0;
end
end
end
always @ (*) begin
if(opCode == 1001) begin
if(in1==-32768) begin
overflow = 1;
end
else
begin
overflow = 0;
end
end
end
always @ (*) begin
case(opCode)
4'b0000: result = in1+in2; //add
4'b0001: result = in1-in2; //subtract
4'b0010: result = in1*5; //mult by 5
4'b0011: result = in1/10; //divide by 10
4'b0100: result = in1&in2; //AND
4'b0101: result = in1^in2; //XOR
4'b0110: result = in1|in2; //OR
4'b0111: result = /*((2^16)-1)-in1;*/(-(in1))-1; //complement
4'b1001: result = in1-1; //decrement
4'b1000: result = in1+1; //increment
endcase
end
endmodule
Failing Testbench Code: (all not listed):
So Im getting the expected value output, however, overflow is equal to 0 when it should be 1. Not sure how I could correct this in my code implementation so all the testcases pass.
in1=0111111111111110 in2=0011001100110010 opCode=0010 result= 0111111111110110 expectedResult= 0111111111110110 overflow=0 expectedOverflow=1
in1= 32766 in2= 13106 opCode= 2 result= 32758 expectedResult= 32758 overflow=0 expectedOverflow=1
in1=0111111111111110 in2=0011001100110011 opCode=0010 result= 0111111111110110 expectedResult= 0111111111110110 overflow=0 expectedOverflow=1
in1= 32766 in2= 13107 opCode= 2 result= 32758 expectedResult= 32758 overflow=0 expectedOverflow=1
Explanation / Answer
I have highlighted a couple of issues :
Should probably be :