Hi I am having trouble with my VHDL code I keep getting this error : Error (1082
ID: 3687287 • Letter: H
Question
Hi I am having trouble with my VHDL code I keep getting this error :
Error (10820): Netlist error at Traffic_Lights.vhd(66): can't infer register for Walk_W because its behavior depends on the edges of multiple distinct clocks
This system is to implement two traffic lights with keys to represent a crosswalk. At the bottom is the code I've created hope you can help me what I can't see.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Traffic_Lights is
port(CLOCK_50 : in std_logic;
Key : in std_logic_vector(3 downto 0);
LEDR : out std_logic_vector(9 downto 0);
LEDG : out std_logic_vector(7 downto 0));
end Traffic_Lights;
architecture behavior of Traffic_Lights is
signal clk : std_logic;
signal Red_N, Yellow_N, Green_N, Walk_N, Red_W, Yellow_W, Green_W, Walk_W : std_logic;
begin
LEDR(8) <= Red_N;
LEDR(7) <= Yellow_N;
LEDG(7) <= Green_N;
LEDR(5) <= Walk_N;
LEDR(1) <= Red_W;
LEDR(0) <= Yellow_W;
LEDG(5) <= Green_W;
LEDR(3) <= Walk_W;
--clk_divider <= 250000000; -- 250MHz being stored in clock divider
--clk_count <= 0;
--Divides 250 MHz signal downto 0.2 Hz
process(CLOCK_50)
Variable clk_divider: integer := 250000000;
Variable clk_count: integer := 0;
begin
if rising_edge(CLOCK_50) then
if (clk_count = clk_divider) then
clk_count := 0;
clk <= '1';
else
clk_count := clk_count + 1;
clk <= '0';
end if;
end if;
end process;
Red_N <= '0';
Yellow_N <= '0';
Green_N <= '1';
Walk_N <= '0';
Red_W <= '1';
Yellow_W <= '0';
Green_W <= '0';
Walk_W <= '0';
process(clk)
begin
if rising_edge (Key(3)) then
--wait until 5000ms;
Green_N <= '0' after 5000ms ;
Yellow_N <= '1';
--wait for 2000ms;
Yellow_N <= '0' after 2000ms;
Red_N <= '1';
--wait for 1000ms;
Red_W <= '0' after 1000ms;
Green_W <= '1';
Walk_N <= '1';
--wait for 3000ms;
for i in 0 to 8 loop
Walk_N <= '0' after 250ms;
--wait for 250ms;
Walk_N <= '1' after 250ms;
--wait for 250ms;
end loop;
Walk_N <= '0' after 3000ms;
--wait for 1000ms;
Green_W <= '0' after 1000ms;
Yellow_W <= '1';
--wait for 2000ms;
Yellow_W <= '0' after 2000ms;
Red_W <= '1';
--wait for 1000ms;
Red_N <= '0' after 1000ms;
Green_N <= '1';
elsif falling_edge (Key(1)) then
--wait for 1000ms;
Walk_W <= '1' after 1000ms;
--wait for 3000ms;
for j in 0 to 8 loop
Walk_W <= '0' after 250ms;
--wait for 250ms;
Walk_W <= '1' after 250ms;
--wait for 250ms;
end loop;
Walk_W <= '0';
--wait for 1000ms;
Green_N <= '0' after 1000ms;
Yellow_N <= '1';
--wait for 2000ms;
Yellow_N <= '0' after 2000ms;
Red_N <= '1';
--wait for 1000ms;
Red_W <= '0' after 1000ms;
Green_W <= '1';
--wait for 5000ms;
Green_W <= '0' after 5000ms;
Yellow_W <= '1';
--wait for 2000ms;
Yellow_W <= '0' after 2000ms;
Red_W <= '1';
--wait for 1000ms;
Red_N <= '0' after 1000ms;
Green_N <= '1';
else
--wait for 5000ms;
Green_N <= '0' after 5000ms;
Yellow_N <= '1';
--wait for 2000ms;
Yellow_N <= '0' after 2000ms;
Red_N <= '1';
--wait for 1000ms;
Red_W <= '0' after 1000ms;
Green_W <= '1';
--wait for 5000ms;
Green_W <= '0' after 5000ms;
Yellow_W <= '1';
--wait for 2000ms;
Yellow_W <= '0' after 2000ms;
Red_W <= '1';
--wait for 1000ms;
Red_N <= '0' after 1000ms;
Green_N <= '1';
end if;
end process;
end behavior;
Explanation / Answer
Below VHDL code can be used to implement traffic lights:
Top Level Entity VHDL Code:
--------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
ENTITY TrafficLightIntersection IS
PORT (CLOCK_50: IN std_logic;
KEY : IN std_logic_vector(1 downto 0);
SW : IN std_logic_vector(0 downto 0);
HEX0 : OUT std_logic_vector(6 DOWNTO 0);
HEX1 : OUT std_logic_vector(6 DOWNTO 0);
HEX2 : OUT std_logic_vector(6 DOWNTO 0);
HEX3 : OUT std_logic_vector(6 DOWNTO 0);
LEDR : OUT std_logic_vector(2 DOWNTO 0);
LEDG : OUT std_logic_vector(2 DOWNTO 0));
END TrafficLightIntersection;
ARCHITECTURE Behavior OF TrafficLightIntersection IS
COMPONENT DecodeHex IS
PORT ( BitInput: IN std_logic_vector(3 DOWNTO 0);
HexOutput: OUT std_logic_vector(6 DOWNTO 0));
END COMPONENT DecodeHex;
COMPONENT ClockCounter IS
GENERIC (UpperBound: integer);
PORT ( Clock: IN std_logic;
Enable: OUT std_logic);
END COMPONENT ClockCounter;
component TrafficControl IS
PORT ( EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;
crosswalktraffic: IN STD_LOGIC;
lowpriortraffic: IN STD_LOGIC;
reset : IN STD_LOGIC;
HIP : OUT STD_LOGIC;
LOWP : OUT STD_LOGIC;
PED : OUT STD_LOGIC;
HiDone : OUT STD_LOGIC;
LowDone : OUT STD_LOGIC;
PedDone : OUT STD_LOGIC;
HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);
LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);
PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
END component TrafficControl;
COMPONENT Edge_Detect is
Port( Clock: IN std_logic;
Enable: IN std_logic;
Input: IN std_logic;
Output: OUT std_logic);
END COMPONENT Edge_Detect;
signal Enable1s : STD_LOGIC;
signal Enable1ms : STD_LOGIC;
signal PedXing : STD_LOGIC;
signal reset : STD_LOGIC;
signal HiCountsig : STD_LOGIC_VECTOR (3 downto 0);
signal LowCountsig : STD_LOGIC_VECTOR (3 downto 0);
signal PedCountsig : STD_LOGIC_VECTOR (3 downto 0);
begin
PedCross: Edge_Detect port map (Clock => CLOCK_50,
Input => KEY(0),
Enable => Enable1ms,
Output=> PedXing);
Rst: Edge_Detect port map( Clock => CLOCK_50,
Input => KEY(1),
Enable => Enable1ms,
Output => reset);
OneSec: ClockCounter Generic map ( UpperBound=>49999999)
port map( Clock => CLOCK_50,
Enable => Enable1s);
OneMilliSec: ClockCounter Generic map( UpperBound=>49999)
port map( Clock => CLOCK_50,
Enable => Enable1ms);
ControlIntersect: TrafficControl port map (EffClock => Enable1s,
Clock => CLOCK_50,
crosswalktraffic => PedXing,
lowpriortraffic => SW(0),
reset => reset,
HIP => LEDG(2),
LOWP => LEDG(1),
PED => LEDG(0),
HiDone => LEDR(2),
LowDone => LEDR(1),
PedDone => LEDR(0),
HiCount => HIcountsig,
LowCount => LOWcountsig,
PedCount => PEDcountsig);
Pedestrian: DecodeHex port map(BitInput => PEDcountsig,
HexOutput => HEX0);
LowPriority: DecodeHex port map(BitInput => LOWcountsig,
HexOutput => HEX1);
HighPriority: DecodeHex port map(BitInput => HIcountsig,
HexOutput => HEX2);
HEX3 <= "1111111"; --Always off--
end Behavior;
Modular Clock Counter Component VHDL Code:
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY ClockCounter IS
GENERIC (UpperBound: integer);
PORT ( Clock: IN std_logic;
Enable: OUT std_logic);
END ClockCounter;
ARCHITECTURE behavior OF ClockCounter IS
signal count : integer range 0 to(UpperBound-1);
BEGIN
PROCESS (Clock)
BEGIN
IF (rising_edge(Clock)) then
IF(count = (UpperBound-1)) then
count <= 0;
Enable <= '1';
else
count <= count+1;
Enable <= '0';
end if;
end if;
END PROCESS;
END behavior;
Modular 7 Segment Display Decoder VHDL Code:
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
ENTITY DecodeHex IS
PORT(
BitInput: IN std_logic_vector(3 downto 0);
HexOutput: OUT std_logic_vector(6 downto 0));
END DecodeHex;
ARCHITECTURE Behavior OF DecodeHex IS
BEGIN
WITH BitInput SELECT
HexOutput <= "1000000" WHEN "0000",
"1111001" WHEN "0001",
"0100100" WHEN "0010",
"0110000" WHEN "0011",
"0011001" WHEN "0100",
"0010010" WHEN "0101",
"0000010" WHEN "0110",
"1111000" WHEN "0111",
"0000000" WHEN "1000",
"0011000" WHEN "1001",
"0001000" WHEN "1010",
"0000011" WHEN "1011",
"1000110" WHEN "1100",
"0100001" WHEN "1101",
"0000110" WHEN "1110",
"0001110" WHEN "1111",
"1111111" WHEN others;
END Behavior;
Modular Edge Detection VHDL File:
--------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Edge_Detect is
Port( Clock: IN std_logic;
Input: IN std_logic;
Output: OUT std_logic);
END Edge_Detect;
Architecture structural of Edge_Detect IS
signal Q1:std_logic;
signal Q0:std_logic;
Begin
Process(Clock)
BEGIN
if (rising_edge (Clock)) then
Q0<=not Input;
Q1<=Q0;
Output <= not(Q0) and (Q1);
END IF;
end process;
end structural;
ControlTraffic VHDL File:
------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity TrafficControl is
PORT (EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;
crosswalktraffic : IN STD_LOGIC;
lowpriortraffic : IN STD_LOGIC;
reset : IN STD_LOGIC;
HIP : OUT STD_LOGIC;
LOWP : OUT STD_LOGIC;
PED : OUT STD_LOGIC;
HiDone : OUT STD_LOGIC;
LowDone : OUT STD_LOGIC;
PedDone : OUT STD_LOGIC;
HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);
LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);
PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
end TrafficControl;
architecture Behavioral of TrafficControl is
type State is (HighPriority, LowPriority, Pedestrian, COUNTDOWN5Ped, COUNTDOWN5Low, L2Ped);
signal CurrentState , NextState : State;
signal countdown9 : std_logic_vector (3 downto 0);
signal countdown4 : std_logic_vector (3 downto 0);
signal countdown5 : std_logic_vector (3 downto 0);
signal resetsig : std_logic;
signal HiEnable : std_logic;
signal LowEnable : std_logic;
signal PedEnable : std_logic;
signal register5 : std_logic;
signal register9 : std_logic;
signal register4 : std_logic;
signal trip5 : std_logic;
signal trip9 : std_logic;
signal trip4 : std_logic;
signal Go2Ped : std_logic;
begin
HiCount <= countdown5;
LowCount <= countdown9;
PedCount <= countdown4;
resetsig <= reset;
Works : process (Go2Ped, reset, CurrentState, countdown4, countdown5, countdown9, NextState, crosswalktraffic, lowpriortraffic, Clock)
begin
case CurrentState is
when HighPriority =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '1';
trip4 <= '1';
trip9 <= '1';
Go2Ped <= '0';
if crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif lowpriortraffic = '1' then
NextState <= COUNTDOWN5Low;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when Pedestrian =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '0';
PED <= '1';
HiDone <= '1';
LowDone <= '1';
PedDone <= '0';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '1';
trip4 <= '0';
Go2Ped <= '0';
if countdown4 = 0 and lowpriortraffic = '1' then
NextState <= LowPriority;
trip4 <= '1';
elsif countdown4 = 0 and lowpriortraffic = '0' then
NextState <= HighPriority;
trip4 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when LowPriority =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '1';
PED <= '0';
HiDone <= '1';
LowDone <= '0';
PEDdone <= '1';
HiEnable <= '0';
LowEnable <= '1';
PedEnable <= '0';
trip9 <= '0';
if countdown9 = 0 and Go2Ped = '0' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif countdown9 = 0 and Go2Ped = '1' then
NextState <= L2Ped;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif crosswalktraffic = '1' then
Go2Ped <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5low =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= LowPriority;
trip5 <='1';
elsif crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when L2Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5<='0';
if countdown5 = 0 then
NextState <= Pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
end case;
end process;
CountDOWN5Down : process (EffClock, HiEnable, resetsig, countdown5, trip5)
begin
if register5 = '1' or resetsig = '1' then
countdown5 <= "0101";
elsif (RISING_EDGE (EffClock)) and HiEnable = '1' THEN
if countdown5 = 0 then
countdown5 <= "0101";
else
countdown5 <= countdown5 - 1;
end if;
end if;
end process;
count9Down : process (EffClock, LowEnable, resetsig, countdown9, trip9)
begin
if register9 = '1' or resetsig = '1' then
countdown9 <= "1001";
elsif (Rising_Edge(EffClock)) and LowEnable = '1' THEN
if countdown9 = 0 then
countdown9 <= "1001";
else
countdown9 <= countdown9 - 1;
end if;
end if;
end process;
count4Down : process (EffClock, PedEnable, resetsig, countdown4, trip4)
begin
if register4 = '1' or resetsig = '1' then
countdown4 <= "0100";
elsif (rising_edge (EffClock)) and PedEnable = '1' THEN
if countdown4 = 0 then
countdown4 <= "0100";
else
countdown4 <= countdown4 - 1;
end if;
end if;
end process;
PROCESS(Clock)
begin
IF Rising_Edge(Clock) THEN
CurrentState <= NextState;
register5 <= trip5;
register4 <= trip4;
register9 <= trip9;
END IF;
END PROCESS;
end Behavioral;