Remaining Time: 1 hour, 50 minutes, 58 seconds. QUESTION 1 What is the decimal v
ID: 3691093 • Letter: R
Question
Remaining Time:
1 hour, 50 minutes, 58 seconds.
QUESTION 1
What is the decimal value of this 16-bit two’s complement number?
-4
12
-12
65532
3.34 points
QUESTION 2
What is the 8-bit two’s complement representation binary value of the decimal number -2?
10000010
11111110
00000010
01111101
3.34 points
QUESTION 3
The addressing mode of the following MIPS instruction (Addi $t1,$t2, 2) is
Register addressing mode
Base displacement addressing mode
Immediate addressing mode
PC-relative addressing mode
3.34 points
QUESTION 4
The following MIPS AND instruction (and $t1,$t2,$t3) will
Perform $t1 and $t2 and store the result into $t3
Perform $t1 and $t3 and store the result into $t2
Perform $t2 and $t3 and store the result into $t1
Perform $t3 and $t1 and store the result into $t2
3.34 points
QUESTION 5
If $t1 = 11, $t2 = 10 and $t3 = 01, what are the final values of these registers after executing the previous MIPS instruction
$t1=00 , $t2=10 , and $t3= 01
$t1=11 , $t2=00 , and $t3= 10
$t1=01 , $t2= 11 , and $t3=00
$t1=01 , $t2= 10 , and $t3= 01
3.34 points
QUESTION 6
What is 5ED4-07A4 when these values represent unsigned 16-bit hexadecimal numbers? The result is in Hexadecimal.
5730
5EA8
5780
0000
3.34 points
QUESTION 7
The following instructions executed by a pipelined processor without forwarding unit. What type of hazard is there?
Add $t0, $s0, $s1
Sub $s2, $t0, $t3
Structural
Control
Structural and Data
Data
3.34 points
QUESTION 8
In the same instructions mentioned above, what is the minimum number of stall cycles that are needed to solve this hazard without using a forwarding unit?
3
1
0
2
3.34 points
QUESTION 9
With a forwarding unit, what is the minimum number of stall cycles that are needed to solve this hazard for the same instructions given above?
0
1
2
3
3.34 points
QUESTION 10
For the following MIPS instruction, what is the minimum number of stall cycles that are needed to solve this hazard with forwarding unit?
LW $t0, 0($t2)
Sub $s2, $t0, $t3
0
1
2
3
3.34 points
QUESTION 11
Branch prediction is a method to solve a pipelining hazard. What kind of hazard this method can be used?
Structural
Control
Structural and Data
Data
3.33 points
QUESTION 12
Assume the individual stages of the datapath have the following latencies:
IF: 250 ps
ID: 350 ps
EX: 150 ps
MEM: 300 ps
WB: 200 ps
Assume the instructions executed by the processor are broken down as follows:
ALU: 45%
Beq: 20%
LW: 20%
SW: 15%
What is the clock cycle time in a pipelined and non-pipelined processor?
Pipelinied: 150ps, Non-pipelined: 1250ps
Pipelinied: 350ps, Non-pipelined: 1250ps
Pipelinied: 300ps, Non-pipelined: 300ps
Pipelinied: 150ps, Non-pipelined: 150ps
3.33 points
QUESTION 13
For the following instructions, what is the minimum stall cycles that are needed after the beq instruction?
Beq r5,r4,label
Add r5,r1,r4
0
1
2
3
3.33 points
QUESTION 14
Suppose that in 1000 memory references there are 40 times misses in the first level cache and 20 misses in the second level cache. What are the various miss rates?
L1 cache miss rate = 4% and L2 miss rate = 50%
L1 cache miss rate = 0.4% and L2 miss rate = 60%
L1 cache miss rate = 4% and L2 miss rate = 60%
L1 cache miss rate = 4% and L2 miss rate = 2%
3.33 points
QUESTION 15
Consider information in question 14 above, assume the miss penalty from L2 cache to the main memory is 200 cycles, the hit time to L2 cache is 10 clock cycles, the hit time of L1 is 1 clock cycle, and there are 1.5 memory references per instruction. What is the average memory access time AMAT?
Given, AMAT = Hit time L1 + Miss rate L1 x (Hit time L2 + Miss rate L2 x Miss penalty L2)
1.56
5.4 Clock Cycles
2.6
6.2
3.33 points
QUESTION 16
For two variables, n=2 , the number of possible Boolean functions is
4
8
16
12
3.33 points
QUESTION 17
The simplest way to determine cache locations in which to store memory blocks is the,
Associative Mapping technique
Direct Mapping technique
Set-Associative Mapping technique
Indirect Mapping technique
3.33 points
QUESTION 18
The sum of -6 and -13 using 2’s complement addition is,
11100011
11110011
11001100
11101101
3.33 points
QUESTION 19
Which one of the following CPU registers holds the address of the instructions (instructions in the program stored in memory) to be executed next?
MAR (Memory address register)
AC (Accumulator)
PC (Program Counter)
IR (Instruction Register)
3.33 points
QUESTION 20
What are the major components of a CPU?
Control Unit, Register Set, Arithmetic Logic Unit
Register Set, Control Unit, Auxiliary Memory
Memory Unit, Arithmetic Logic Unit, Auxiliary Memory
Register Set, Control Unit, Memory Unit
3.33 points
QUESTION 21
__________ is the memory usually written by the manufacturer.
RAM
ROM
DRAM
SRAM
3.33 points
QUESTION 22
A page frame is also called as ________________.
Print document
Block
Disk
Hit
3.33 points
QUESTION 23
The performance of the cache memory is measured in terms of a quantity called _________________
Initialization Ratio
Address Ratio
Hit Ratio
Miss Ratio
3.33 points
QUESTION 24
Mean Time Between Failures MTBF, Mean Time To Replacement MTTR, and Mean Time to Failure are useful metrics for evaluating the reliability and availability of storage sources. Given the following calculate the MTBF?
The MTTF is 3 years and the MTTR is 1 day.
1096 days
2000 days
1 year
1095 days
3.33 points
QUESTION 25
Multiprocessor network topologies are
bus, mesh, ring
SISD, MIMD
multithread, multicore
clusters and scale computers
3.33 points
QUESTION 26
Translate unsigned 0xabcdef12 into decimal. The answer is
235212365
265423622
2882400018
-521233652
3.33 points
QUESTION 27
Assume the following register contents:
$t0=0xAAAAAAAA, $t1= 0x12345678
What is the value of $t2 after the following set of instructions?
Sll $t2,$t0,4
Andi $t2,$t2,-1
0xAAAAAAA0
0x0AAAAAAA
0xBBBBBBBB
0xBABABABA
3.33 points
QUESTION 28
When processor designer consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a datapath, where we have I-Mem, Regs, Control, ALU, D-Mem, 2 Add units and 3 Mux units. A single unit of each I-Mem, Add, Mux, ALU Regs, D-Mem, and control blocks have latencies of 400, 100, 30, 120, 200, 350, and 100 ps, respectively and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively.
Consider the addition of a multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction.
What the clock cycle time without this improvement? (consider the critical path only)
1130 ps
2000 ps
1500 ps
1300 ps
3.33 points
QUESTION 29
What the clock cycle time with this improvement?
2300 ps
1430 ps
1600 ps
1800 ps
3.33 points
QUESTION 30
What is the new cost with this improvement?
4600
5800
4490
3360
3.33 points
Click Save and Submit to save and submit. Click Save All Answers to save all answers.
Description Instructions Timed Test This test has a time limit of 2 hours.This test will save and submit automatically when the time expires.Warnings appear when half the time, 5 minutes, 1 minute, and 30 seconds remain. Multiple Attempts Not allowed. This test can only be taken once. Force Completion This test can be saved and resumed at any point until time has expired. The timer will continue to run if you leave the test.
Explanation / Answer
6.5730
7.Control hazards
11.Control hazards
12.Pipelined: cycle time determined by slowest stage: 350ps.
Non-pipelined: cycle time determined by sum of all stages: 1250ps
16)16
17) Direct mapping
18) 11101101
19) program counter
20) Control Unit, Register Set, Arithmetic Logic Unit
21) ROM
22) block
23) Hit Ratio
25)bus,ring,mesh
26)2882400018
28)1300ps
29)1430ps
30)4490
Note : .need explanation let me know