Please show your work Consider a CPU that implements two parallel fetch-execute
ID: 3696037 • Letter: P
Question
Please show your work
Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming the instruction cycle below:
a one clock cycle fetch
a one clock cycle decode
a three clock cycle execute
and a 50 instruction sequence:
No pipelining would require _____ clock cycles:
b) A scalar pipeline would require ____ clock cycles:
c) A superscalar pipeline with two parallel units would require ______ clock cycles:
show your work
Explanation / Answer
According to the above information if its a non pipelined processor, then that requires 3 clock cycles per instruction. So the total clock cycles = 3 x 50 = 150 Clock cycles for the instruction sequence.
When pipelined, it requires 50 x 1 = 50 clock cycles
when you implement 3 x super scalar pipeline, it requires 50 x 1/3 = 16 clock cycles