Consider the following verilog module description. {{{{{module weird; reg [3:0]
ID: 3697782 • Letter: C
Question
Consider the following verilog module description.
{{{{{module weird; reg [3:0] a; always @(a) begin a <= #15 a + 2; #7 a <= a - 1; end always @(a) $display("$time=%d,a=%d",$time,a); initial begin a = 0; #20 $display("$time=%d,a=%d",$time,a); #2 a = 5; #20 $display("$time=%d,a=%d",$time,a); $finish; end endmodule}}}
Determine what the exact output of the simulator would be. Note: You may simulate the above code on the verilog simulator and examine the output. But that is not enough. Give a clear explanation of the sequence of actions that the simulator would perform to produce the outputs.
Explanation / Answer
module weird;
reg[3:0] a;
always @(a)
begin
a<=#15 a + 2;
#7 a <= a-1;
End
always @ (a)
$display(“$time=%d, a=%d”, $time, a);
initial
Begin
A=0;
#20 $display(“$time=%d, a=%d”,$time,a);
#20 a=5;
#20 $display(“$time=%d, a=%d”,$time,a);
$finish;
End
endmodule
This code does not provide output...its shows the error..