Consider the following verilog blocks that are part of a module description. {{{
ID: 3697783 • Letter: C
Question
Consider the following verilog blocks that are part of a module description.
{{{always @(a or b or c) $display("$time=%d,a=%d,b=%d,c=%d",$time,a,b,c); always @(a or b) STATEMENT A; (see below) initial begin a = 5; b = 2; #3 a = 8; #20 $finish; end; }}}
Consider the following four variations of STATEMENT A.
1. #12 c = a + b;
2. c = #12 a + b;
3. #12 c <= a+b;
4. c <= #12 a+b;
For each of the cases above, determine what the exact output of the simulator would be. Note: running a simulator and presenting the output is not enough. Give a clear explanation of the sequence of actions that the simulator would perform to produce the outputs.
Explanation / Answer
Given that
initial
begin
a=5;
b=2;
# 3 a=8;
# 20 $ finish;
end;
1ans)
from STATEMENT A
we consider the above given code
it initially prints 'a' and 'b' values from above code
then
# 12 c=a+b;
it blocks for 12 times units after assigns the values of a and b as a=5, b=2, after blocking then it adds values of a and b, then the summation value is to be assigned to 'c'
2ans)
a and b values are to be considered from STATEMENT A
c=# 12 a+b;
it defines that, it evalutes the value of c after assigning the a and b values, schedules c=0 in 12 time units and go to next line for execution
3ans)
#12 c<=a+b;
It can be executed concurrently.
4ans)
c<= #12 a+b;