Please fill in all 3 blanks. Thanks QUESTION 5 Cache performance Suppose a compu
ID: 3719260 • Letter: P
Question
Please fill in all 3 blanks. Thanks
QUESTION 5 Cache performance Suppose a computer system has a 5-stage MIPS processor, and separate data and instruction caches. The hit time of both caches is one cycle. The miss penalty of both caches is 80 cycles. When the processor 35% of the instruction executed n an application are memory accesses runs an application, the miss rate of the data cache s 10% and the miss rate of he instruction cache is 59 Keep one digit and only one digit after the decimal point. For example, enter 5.0 for both 5 and 5.06 The overhead of CPl from data memory accesses is The overhead on CPl from instruction memory accesses is If the CPI for the application is 1.6 without memory stalls, the overall CPI with memory stalls isExplanation / Answer
SOLUTION:
1. Average memory access time of data cache = hit time + (miss rate * miss penality)
=> 1 + (0.1 * 80)
=> 1 + 8.0
=> 9.0
The average memory access time of data cache 9.0
2. The average memory access time of the instruction cache = hit time + (miss rate * miss penality)
=> 1 + (0.05 * 80)
=> 1 + 4.00
=> 5.0
The average memory access time of the instruction cache = 5.0