Individual stages of the data path have the following latencies: [2 × 6] IF ID E
ID: 3719436 • Letter: I
Question
Individual stages of the data path have the following latencies: [2 × 6] IF ID Exe Mem WB 250ps 350ps 150ps 300ps 200ps Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 45% 20% 20% 15% a. What is the clock cycle time in a pipelined and non-pipelined processor? b. What is the total latency of an LW instruction in a pipelined and non-pipelined processor? c. If we can split one stage of the pipelined data path into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? d. Assuming there are no stalls or hazards, what is the utilization of the data memory? e. Assuming there are no stalls or hazards, what is the utilization of the write-register port of the ”Registers” unit? f. Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction ?nishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with single cycle, multi-cycle, and pipelined organization.
Explanation / Answer
Solution:
Note: The first four subparts have been answered as per Chegg guidelines, please repost others.
a)
In the non-pipelined, each of the instruction time will take its own cycle time
so total cycle time will be
= 250+350+150+300+200
=1250 ps
Pipelined:
In pipelined the instruction with the maximum value will be taken into consideration because that will be the time which is maximum and within that time all the instruction will be done parallelly, which means cycle time will be
= 350 ps
b)
LW instruction uses all 5 stages.
The pipelined processor takes 5 cycles at 300 ps per cycle for the total latency of 1800 ps.
The non-pipelined processor takes 1250 ps.
c)
Split Memory Access stage into two stages of 150 ps. New clock cycle time is 150 ps.
d)
Assuming there are no stalls or hazards,
LW and SW instructions use the data memory. As a result, the utilization of the data memory
is 20% + 15% = 35%.
Similarly, ALU and LW instructions use the register block’s write port. As a result, the
utilization of the register block’s write port is 45% + 20% = 65%.
I hope this helps if you find any problem. Please comment below. Don't forget to give a thumbs up if you liked it. :)