I have the following code for VHDL that is supposed to make the 50 MHz clock app
ID: 3726394 • Letter: I
Question
I have the following code for VHDL that is supposed to make the 50 MHz clock appear as 1 Hz with a clock divider but it isn't working any clue on what is wrong?
CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FourbitBCD is
port (clock, reset: inout std_logic;
A, B, C, D: inout std_logic);
end FourbitBCD;
architecture behavior of fourbitBCD is
signal clock_out: std_logic;
signal count,extra: integer:=1;
signal i: integer:=0;
signal n: integer:=0;
signal tmp : std_logic := '0';
begin
while(n=1) loop
process(clock,reset) is
begin
if(reset='1') then
count<=1;
tmp<='0';
elsif(clock'event and clock='1') then
while(count < 50000000) loop
count<= count + 1;
end loop;
extra <= extra + 1;
clock_out <= tmp;
end if;
count<=0;
end process;
process(extra)
begin
if(i=10) then
i<=0;
end if;
case i is
when 0 =>
A<= '0';
B<= '0';
C<= '0';
D<= '0';
when 1 =>
A<= '0';
B<= '0';
C<= '0';
D<= '1';
when 2 =>
A<= '0';
B<= '0';
C<= '1';
D<= '0';
when 3 =>
A<= '0';
B<= '0';
C<= '1';
D<= '1';
when 4 =>
A<= '0';
B<= '1';
C<= '0';
D<= '0';
when 5 =>
A<= '0';
B<= '1';
C<= '0';
D<= '1';
when 6 =>
A<= '0';
B<= '1';
C<= '1';
D<= '0';
when 7 =>
A<= '0';
B<= '1';
C<= '1';
D<= '1';
when 8 =>
A<= '1';
B<= '0';
C<= '0';
D<= '0';
when others =>
A<= '1';
B<= '0';
C<= '0';
D<= '1';
end case;
i <= i + 1;
end process;
end loop;
end behavior;
Explanation / Answer
Clock Divider is also called as Frequency Divider. Here we are using a count value to Produce the dealy for the Output and we can produce different clcok frequencies using the count values. Here if we give count as 1 then the we are providing the delay for 1 time means the frequency of the signal become half = 25MhZ
Then for 10 Hz the count would be 2500000 and for 1 Hz the count os 25000000
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE>numeric_std.ALL;
entity clockdivide is
port (clk,reset,SW0: in std_logic;out_clock:out std_logic);
end clockdivide;
architecture divide of clockdivide is
signal count : integer :=1;
signal tmp: std_logic:= '0';
begin
process(clk,reset,SW0)
begin
if (SW0==0) then
if (reset='1') then
count<=1;
tmp<= '0';
elsif (clk event and clk='1')
count <=count +1;
if (count ==2500000) then
tmp <=NOT tmp;
count <=1;
end if;
end if;
elsif(SW0==1)
if (reset='1') then
count<=1;
tmp<= '0';
elsif (clk event and clk='1')
count <=count +1;
if (count ==25000000) then
tmp <=NOT tmp;
count <=1;
end if;
end if;
end if;
coutclock <=tmp;
end process;
end divide;