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The figure below shows the state diagrams of two possible cache coherence protoc

ID: 3776473 • Letter: T

Question

The figure below shows the state diagrams of two possible cache coherence protocols maintained at cache i. Deduce and explain each protocol and compare each to MESI (Modified, Exclusive, Shared, Invalid).

W(i) = Write to line by processor i

R(i) = Read line by processor i

Z(i) = Displace line by cache i

W(j) = Write to line by processor j (j ? i)

R(j) = Read line by processor j (j ? i)

Z(j) = Displace line by cache j (j ? i)

Invalid WG), RG), ZG) Valid WG), Z(i) R(i) Invalid W(i) WU), Z(i) xclusiv W(i) R(i), ZG) Shared write-through W(i)

Explanation / Answer

Modified(M)

The cache line is present only in the current cache, and is dirty - it has been modified(M state) from the value in main memory. The cache is required to write the data back to main memory at some time in the future, before permitting any other read of the (no longer valid) main memory state. The write-back changes the line to the Shared state(S).

Exclusive(E)

The cache line is present only in the current cache, but is clean - it matches main memory. It may be changed to the Shared state at any time, in response to a read request. Alternatively, it may be changed to the Modified state when writing to it.

Shared(S)

Indicates that this cache line may be stored in other caches of the machine and is clean - it matches the main memory. The line may be discarded (changed to the Invalid state) at any time.

Invalid(I)

Indicates that this cache line is invalid (unused).

write-back caches

  the process of restoring to profit a provision for bad or doubtful debts previously made against profits and no longer required.

write through cache

  Write through is a storage method in which data is written into the cache and the corresponding main memory location at the same time. The cached data allows for fast retrieval on demand, while the same data in main memory ensures that nothing will get lost if a crash, power failure, or other system disruption occurs.