Answer the following question in Bold letters using the information provided: Su
ID: 3802972 • Letter: A
Question
Answer the following question in Bold letters using the information provided:
Suppose the following sequence of instructions executes on a system with a TLB(Translate lookaside buffer) of infinite size that is initially empty.
load 4096, r1
load 4100, r2
Executing this fragment requires eight operations:
1. Translating the address of the first instruction
2. Fetching the first instruction
3. Translating the address of the first data location (4096)
4. Reading the first data value
5. Translating the address of the second instruction
6. Fetching the second instruction
7. Translating the address of the second data location (4100)
8. Reading the second data value
If the system has no TLB(Translate lookaside buffer), each of these operations requires a memory access. How many memory accesses are required if the system does have a TLB?
You may assume that both instructions are located on the same page. The virtual address locations 4096 and 4100 are also located on one page, which is different from the page that contains the instructions. The TLB is initially empty.
a TLB of infinite sine that is ini lly empty. Esecuting this fragaert requires eight operations. Tranelating the address of the fired imestraction Fetching the instruction 3 Translating the address of the first data location (4036 Reading the data value g the adklrex or the Record inst uction Fetching the second instruction 7. Translating the address of the secoed data locatie (4100) & Reading the second data value If the system has no TLB each of those operatios requiar amesmory access. ory are requind if the y tem doen have a TIB You may areame that both instrartions are located on the same page, The virtual address locations 4096 aud 4100 are also located on one page, which different from the page that contains the instructions. The TLBisinitiallyExplanation / Answer
When an address is searched in the TLB and not found, the physical memory must be searched with a memory page crawl operation. As virtual memory addresses are translated, values referenced are added to TLB. When a value can be retrieved from TLB, speed is enhanced because the memory address is stored in the TLB on processor. Most processors include TLBs to increase the speed of virtual memory operations through the inherent latency-reducing proximity as well as the high-running frequencies of current CPU’s.
TLBs also add the support required for multi-user computers to keep memory separate, by having a user and a supervisor mode as well as using permissions on read and write bits to enable sharing.
Offset
The last bits of the virtual address are called the offset which is the location difference between the byte address you want and the start of the page. You require enough bits in the offset to be able to get to any byte in the page. For a 4K page you require (4K == (4 * 1024) == 4096 == 212 ==) 12 bits of offset. Remember that the smallest amount of memory that the operating system or hardware deals with is a page, so each of these 4096 bytes reside within a single page and are dealt with as "one".
Virtual Address Translation
Virtual address translation refers to the process of finding out which physical page maps to which virtual page.
When translating a virtual-address to a physical-address we only deal with the page number. The essence of the procedure is to take the page number of the given address and look it up in the page-table to find a pointer to a physical address, to which the offset from the virtual address is added, giving the actual location in system memory.
Since the page-tables are under the control of the operating system, if the virtual-address doesn't exist in the page-table then the operating-system knows the process is trying to access memory that has not been allocated to it and the access will not be allowed.
Assuming page is not in memory. The process will be along the lines of the following. There will be 0 seconds to access TLB cache for the entry for page P. This will result in a miss so the page table for this process will be accessed. Assume the page table is in memory. It’ll take 0.1 ns to access the page table and get the entry. Since page P is not in memory, the entry will be invalid. It’ll take 1 ms to get the page from disk into memory. Then another 0.1 ns to get page P from memory. So in total, it’ll take 1000000.2 ns.