Caching Problems Make sure you understand the slides related to caching and all

Question

Caching Problems Make sure you understand the slides related to caching and all problems related to caching on the Definitions: cache e size and ock size s number of bits required to address all memory blocks r er of bits required to address all cache lines w- number of bits required to address all units within a cache line (or memory block) Direct Mapping: l J 96 m where I cache line J block number (not the address) number of cache lines The first thing to do for these kinds of problems is to calculate the values for s, r and w for the given system. For the first set of problems assume the following system configuration: Main Memory consists of 1024 bytes and the system is byte addressable The caching logic interprets the 1024 bytes of memory as a set of blocks, each of which is 4 bytes. There are 16 cache lines. Compute s, the number of bits necessary to uniquely address all memory blocks. Memory has a total of 1024 bytes divided into blocks of 4 bytes. The number of blocks is thus 2410 242 248. Given 248 blocks, s 8. Compute r, which is the number of bits needed to uniquely address each cache line. There are 16 244 cache lines and therefore r 4. Compute w, which is the number of bits required to uniquely address each byte within a given block. Block size K 4- 242 thus w 2. In direct-mapped caches, the TAG is the most significant s r bits of the address, the LINE is the next r bits, and the offset is the least significant w bits of the address. All questions count 4 points each.

Explanation / Answer

1) block 0

i=j%m

here j=0 (block number)

m=16 (total cache lines)

so i=0%16 =0

i=0th cache line this block is moved.

-----------------------------------------------------------

block 251

similarly

j=251

m=16

i=j%m => i=251%6

i=5 th cache line it is placed.

------------------------------------------------------------------

block 6

j=6 and m=6

so i = 6%6 =0

---------------------------------------------------------------------------------------

3)

cache lilne number memory blocks

0th 0,6,12,18,................. (6*p where p=0,1,2,3 and 6*p <=256)

1 1,7,13,19,.................(6*p+1 ere p=0,1,2,3 and 6*p +1<=256)

2 2,8,14,20,..................(6*p+2where p=0,1,2,3 and 6*p+2 <=256)

3 3,9,15,21 .................(6*p+3where p=0,1,2,3 and 6*p+3 <=256)

4 4,10,16,22,...............(6*p+4where p=0,1,2,3 and 6*p+4 <=256)

5 5,11,17,23,.................(6*p+5where p=0,1,2,3 and 6*p+5 <=256)

---------------------------------------------------------------------------------------------------------------------------

q.5)

1000110011 (given addresss)

we know that

s=8,r=4,w=2

tag=s-r =4

line=r=4

offset=w=2

tag bit is most significnat bits

line bits are next r bits of tag

and offset is next least significant bits of line

so tag bits =1000

line bits=1100

offset bits=11 of given address

Related Questions

Navigate

• Browse (All)
• Browse C
• Subjects

---