Consider the following sequence of instructions, and assume that it is executed
ID: 3807625 • Letter: C
Question
Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined data-path, address the problems a) and b) below: add r5, r2, r1 lw r3, 4(r5) lw r2, 0(r2) or r3, r5, r3 sw r3, 0(r5) If there is no forwarding or hazard detection, insert nops to ensure correct execution. Repeat a) but now use nops only when a hazard cannot be avoided by changing or rearranging instructions. Assume r7 can be used to hold temporary values in your modified code. Comment whether there is a gain in performance or not, and why.Explanation / Answer
a)
There is a data hazard between the first pair of instructions add and lw because of register r5. The result of add instruction is stored in r5 which is used in the lw instruction. so we need to insert nops. Also there is a dependency between lw r3 and or instruction where the result of r3 is used in or instruction.
modified code will be:
add r5,r2,r1
nop
nop
nop
lw r3,4(r5)
lw r2,0(r2)
nop
nop
or r3,r5,r3
sw r3 ,0(r5)
b)
In this case we can do the rearrange of the instructions since lw r2 instruction does not have any dependency on anything and we can use r7 register for storing lw r3 operation to avoid hazard with or instruction.
modified code will be
add r5,r2,r1
lw r2,0(r2)
nop
nop
lw r7,4(r5)
or r3,r5,r7
sw r3,0(r5)
Here we have removed both the hazards with the usage of r7.
c)
Yes there is a significant gain in performance as we have removed 3 nops from the code in part a in part b.
Ultimately saving 3 clock cycles in completion of entire code on pipelined processor.