Consider the following sequence of instructions executed on the basic 5 stage pi
ID: 672238 • Letter: C
Question
Consider the following sequence of instructions executed on the basic 5 stage pipeline...
add $t3, $t2, $t1
or $t5, $t3, $t4
andi $t6, $t7, $t4
add $t7, $t2, $t1
a) Assuming our processor has no forwarding or hazard detection, insert a minimal amount of pipeline stalls to ensure correct execution (you may stall the pipeline with the instruction add $zero, $zero, $zero).
b) Assuming our processor has no forwarding or hazard detection, rearrange the instructions and add stalls only if necessary to ensure proper execution. The values contained in the registers after executing your modified code should be equivalent to the unmodified execution.
Explanation / Answer
a) Assuming our processor has no forwarding or hazard detection, insert a minimal amount of pipeline stalls to ensure correct execution (you may stall the pipeline with the instruction add $zero, $zero, $zero)
Solution:
Since it is a five stage processor pipeline there is a dependency for the first set of instructions. From register 3 is written by add instruction and same register is used as an operand by the next or instruction. To solve the dependency we need to insert two nop instructions in the pipeline so that r3 updates are available for next instruction. Similar is the case with next set of instructions.
Code:
add $t3, $t2, $t1
nop
nop
or $t5, $t3, $t4
andi $t6, $t7, $t4
nop
nop
add $t7, $t2, $t1
b) Assuming our processor has no forwarding or hazard detection, rearrange the instructions and add stalls only if necessary to ensure proper execution. The values contained in the registers after executing your modified code should be equivalent to the unmodified execution.
Solution:
We can solve the problem by re-arranging the instructions as there is no direct dependency between them.We need to insert two nop to avoid hazards.
Code:
add $t3, $t2, $t1
andi $t6, $t7, $t4
nop
or $t5, $t3, $t4
nop
add $t7, $t2, $t1