Consider the full datapath of a single cycle design as shown in the diagram: Rec
ID: 3812966 • Letter: C
Question
Consider the full datapath of a single cycle design as shown in the diagram: Recall that ALUOp specifies two bits for: R-format instrs.(10), SW/LW instrs.(00), and BEQ instrs (01). Each instruction below is followed by a set of control signals. Indicate the state of each of the control signals as needed for the successful execution of the corresponding instruction. (a) OR $t1, $t2, $t3 RegDst: Reg Write: ALUSre: ALUOp: MemtoReg: (b) beq $t1, $t2, xlabel Branch: ALUSre: ALUOp: (c) lw $t1, 200($s1) RegDst: RegWrite: ALUsre: ALUOp: MemRead: MemtoReg:Explanation / Answer
a) OR $t1, $t2, $t3
RegDst: 1 RegWrite: 1 ALUSrc: 0 ALUOp: 10 MemtoReg: 0
b) beq $t1, $t2, xlabel
Branch: 1 ALUSrc: 0 ALUOp:01
c) lw $t1, 200($s1)
RegDst: 0 RegWrite: 1 ALUSrc:1 ALUOp: 00 MemRead:1 MemtoReg: 1