Consider the example of an unpipelined processor shown in Figure 1 We assume tha
ID: 3817505 • Letter: C
Question
Consider the example of an unpipelined processor shown in Figure 1 We assume that the combinational logic requires 300 ps (picoseconds) to process any computation and the loading of the results in the register requires 20 ps. The maximum rate at which we could operate in this system, also called as the throughput, is given by the following formula 1 instruction 1000 picosecond (1) Throughput s 3.12 GIPS. (20 300 picosecond 1 nanosecond where GIPS stands for giga-instructions per second. The total time required to perform a single instruction from beginning to end is known as the latency. In this system, the latency is 320 ps. Thus, Throughput (in GIPS) latency (in picoseconds x 1000. Also note that each instruction I1, 12 and 13 thus requires latency ps to process completely. Suppose we divide the computation performed by our system in three stages A, B and C (see Fig. 2), where each requires 30 100 ps. Then we could put pipeline registers between the stages so that each instruction moves through the system in three steps, requiring three complete clock cycles from beginning to end. In this system, we could cycle the clocks every 100 20 120 picoseconds, giving a throughput of around 8.33 GIPS. Since processing a single instruction requires 3 clock cycles, the latency of this pipeline is 3 x 120 360 ps. 20 ps 300 ps Combinational e Delay 320 ps logic Throughput 3.12 GIPS Clock (a) Hardware: UnpipelinedExplanation / Answer
Given :
No of stages =6
Computation time =300ps and overhead for each register =20ps
To find : Latency =?
Throughput=?
Now, Computation time for each stage =300/6=50ps
So cycle of clocks =50+20=70ps at each stage
Since processing single instructions require 6 cycles so
Latency=6X70=420ps
and Throghput= 1/latency * 1000=1/70*1000=14.29GIPS