Consider an unpipelined or single-stage processor design. At the start of a cycl
ID: 3840522 • Letter: C
Question
Consider an unpipelined or single-stage processor design. At the start of a cycle, a new instruction enters the processor and is processed completely within a single cycle. It takes 1,000 ps to navigate all the circuits in a cycle. Therefore, for this design to work, the cycle time has to be at least 1,000 pico seconds.
a) What is the clock speed of this processor?
b) What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache? (The instruction/data cache ensures that there are no latencies involved in fetching from additional on-board memory).
c) What is the throughput of this processor (in billion instructions per second)?
Explanation / Answer
a.
It is given that every clock cycle a new instruction enters the processor and the instruction takes 1000ps
since the processor is not pipelined, only one instruction can be handled by the processor for a given clock cycle.
So we can infer that the time period of the clock is atleast 1000ps or 10-9 sec
Therefore (if you remember your physics classes) frequency is atmost = 1/time period = 109 Hz or 1GHz
So the clock period is <=1GHz
b.
Since its mentioned that at the start of a cycle, a new instruction enters the processor and is processed completely within a single cycle, ideal CPI should be 1.
c.
in 1000ps it processes 1 instruction, therefore in 1sec it processes 109 instuctions (this is the throughput).