Imagine the new instruction SUB, meaning subtract, has been added to the ISA of
ID: 3916016 • Letter: I
Question
Imagine the new instruction SUB, meaning subtract, has been added to the ISA of Figure 6.2. The assembly language instruction SUB R1, R2, R3 is defined as R1 <- R2 – R3 where R2 is the minuend (the operand being decreased) and R3 is the subtrahend (the amount of the decrease). Write a descriptor in the format shown in Figure 6.2 for all bit strings that mean SUB R1, R2, R3. For any field in the binary representation of this assembly language instruction that is not a unique bit string, write a simple specification of all acceptable bit strings.
operation reg A reg B dst reg unused add 0 0001 operation reg A unused dst reg offset load o 001 operation reg A reg B unused offset store o 001 operation reg A unused unused offset ump o 01 0 0 Figure 6.2 The binary representation for each of the four instructions listed in Figure 6.1. Each instruction is thirty-two bits longExplanation / Answer
Instruction format for the instruction SUB R1, R2, R3 :
In instruction SUB R1, R2 , R3
R1 is the destination register , R2 and R3 are regA and regB respectively.
SUB will have opcode of 5bits and it's value will be greater than 4 as 00001 is reserved for add, 00010 for load , 00011 for store and 00100 for jump instruction.
R2 has binary value of 0010
R3 has binary value of 0011
R1 is a CPU register.
So, descriptor in the format shown for all bit string that mean SUB R1,R2,R3 :
operation regA regB dst reg offset 5bits 4bits 4bits 4bits 15bits