I. Stack. II. Memory locations. III. I/O registers A- I and II B- I and III C- I

Question

I. Stack. II. Memory locations. III. I/O registers A- I and II B- I and III C- II and III D- All of the above
2- Operand Forwarding is:
A- A hardware modification of datapath to overcome the problem of data dependency
B- A software implementation of memory delays
C- A hardware implementation of memory delays
D- none of the above

3- In pipelining, the following two RISC instructions does not create dependencies regardless of the used registers: A- A store instruction followed by an Add instruction. B- An unconditional branch instruction followed by a Subtract instruction. C- A store instruction followed by a Load instruction D- All of the above
4- Why the CISC instruction LOAD R5, ( R7)+ cannot be executed on the RISC hardware of Figure 1: A- Because it has data dependency B- Because it requires indirect addressing C- Because it requires updating two registers D- All of the above
5- A RISC processor, which uses the five steps sequence in Figure 1, is driven by 1 GHz clock. How many nanoseconds are required to execute a STORE instruction if access to the memory is always completed in 2 clock cycles? A- 9 B- 7 C- 6 D- 5

Figure 1 Address C Register tle Address A RA RB Immediate value MuxB lnA ALO Out RM Memory data Returnaktres MusY RY

Explanation / Answer

1. D

2. C

3. B

4. D

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