Use the following single-cycle MIPS CPU design as the baseline for this question
ID: 674397 • Letter: U
Question
Use the following single-cycle MIPS CPU design as the baseline for this question. It supports R-format ALU, lw, sw, beq, and j instructions.
1) Extend the baseline to support the slti instruction. Check Appendix A (from Computer Organization and Design: The Hardware/Software Interface, 5th Ed. by David A. Patterson and John L. Hennessy) for the instruction format of slti.
a) Itemize the changes to the datapath, the control unit, and the ALU control. Those may include any new connections, new datapath elements, revision of an existing datapath element, new/extended control signal(s), and change to the internal logic (truth table) of the control unit and/or the ALU control. If you wish, you may mark your change on the figure. Hint: You may print the figure, hand-mark your changes, and then take a picture and insert it into the file.
b) Decide the control signal values for the jr instruction. The following table shows the setting of control lines (signals) for the baseline design. Revise the table as needed.
Explanation / Answer
a) slti instruction format:
b)There is NO change required to the control signal table, because jr is a R-type instruction.