Consider the circuit shown below. The blocks A, B, and C represent combination l
ID: 1480775 • Letter: C
Question
Consider the circuit shown below. The blocks A, B, and C represent combination logic blocks with the following properties: tlogic,minA = 200 pS, tlogic.maxA = 1 nS tlogic.minB = 300 pS, tlogic,maxB = 2 nS tlogic.minC = 100 pS, tlogic.maxC = 0.5 ns The blocks labeled L arc positive latches clocked by 0. The latches arc transparent when Phi is high. Both the latches arc identical and have a setup-time of tsu = 150ps and d-q delay tclk-q = 250 ps. The clock-to-q delay is thold = 100ps, and the hold time is thoid = 100 ps. The clock has a period Tcik and is high for a duration of ToN Determine the conditions on the clock necessary to avoid hold-time violations. Determine the absolute minimum clock period for this circuit to work correctly as well as the maximum duty cycle. Suppose that due to clock skew the clock signal at LI arrives 100ps earlier than the clock signal at L2. Calculate the absolute minimum clock period for this circuit to work properly?Explanation / Answer
(a) The conditions on the clock necessary to avoid hold-time violations which is given as :
there are two possible paths for this condition namely as,
L1 - A - C - L2 and L2 - B - C - L2
using an equations, we have
tclk-q + tlogic,minA + tlogic,minC > Ton + thold { eq.1 }
inserting the values in above eq.
(100 ps) + (200 ps) + (100 ps) > Ton + (100 ps)
Ton < (400 ps) - (100 ps)
Ton < 300 ps
(b) The absolute minimum clock period for this circuit to work correctly as well as the maximum duty cycle which is given as :
using an equation, we have
tclk-q + tlogic,maxB + tlogic,maxC + tsetup < Tclk { eq.2 }
inserting the values in eq.2,
(100 ps) + (2 ns) + (0.5 ns) + (150 ps) < Tclk
Tclk > 2.75 ns
And the maximum duty cycle of the clock is given by -
(Ton,max / Tclk,min) x 100%
[(300 ps) / (2.75 ns)] x 100%
(0.109) x 100% = 10.9 %
(c) The absolute minimum clock period for this circuit to work properly which is given as :
using an equation, we have
-tskew + tclk-q + tlogic,minA + tlogic,minC > Ton + thold { eq.3 }
inserting the values in eq.3,
- (100 ps) + (100 ps) + (200 ps) + (100 ps) > Ton + (100 ps)
(300 ps) > Ton + (100 ps)
Ton < (300 ps) - (100 ps)
Ton < 200 ps
And the maximum duty cycle of the clock is given by -
(Ton,max / Tclk,min) x 100%
[(200 ps) / (2.75 ns)] x 100%
(0.0727) x 100% = 7.27 %