Memories have become one of the most commonly used building blocks in ASIC desig
ID: 2079650 • Letter: M
Question
Memories have become one of the most commonly used building blocks in ASIC designs. For conventional ASIC design flows, the ASIC vendor supplies customers with embedded memories as well as the placement & routing of the whole ASIC chip.
For Customer Own Tooling (COT) type of ASIC design, the designer is responsible to get his own memories. The ASIC designers either design their own memories or buy memory blocks from a third party vendor.
Design a memory model with the following features:
128 words by 32 bits
Two read/write ports
Both read/write operations are synchronous
The memory contain the following control pins:
wea, web: write enable, which controls the write
mea, meb: memory enable must be high for both read and write operations.
clka, clkb: clocks
adra, adrb : address
qa, qb: memory outputs
da, db: memory inputs
The following is the module outline:
module ram128x32 (QA, QB, ADRA, ADRB, DA, DB, WEA, WEB, MEA, MEB, CLKA, CLKB);
…
endmodule
You will need to do the following:
Write the behavior module
Create a test fixture for the module
Show that your memory model works properly for both read & write operations
Explanation / Answer
Verilog code:
Module ram128*32(addr_0,addr_1,data_in0,data_in1,data_out0,data_out1,CS_0,CS_1,WR,OE,clk,rst);
parameteraddr_width=128;
parameterdata_width=32;
parameter depth=8;
input [addr_width-1:0]addr_0,addr_1;
input [data_width-1:0]data_in0,data_in1;
input CS_0,CS_1,WR,OE,clk,rst;
output [data_width-1:0]data_out0,data_out1;
reg [data_width-1:0]d_out0,d_out1;
reg [data_width-1:0]mem[depth-1:0];
integer i;
always @(posedgeclk)
begin
if(rst)
begin
for(i=0;i<=depth-1;i=i+1)
begin
mem[i]=0;
end
end
else if (CS_0)
begin
if (WR) mem[addr_0]=data_in0;
else d_out0=mem[addr_0];
end
if (CS_1)
begin
if (WR) mem[addr_1]=data_in1;
else d_out1=mem[addr_1];
end
end
assign data_out0=(CS_0 && OE && ~WR) ? d_out0 : 8'hz;
assign data_out1=(CS_1 && OE && ~WR) ? d_out1 : 8'hz;
endmodule
Module ram128*32(addr_0,addr_1,data_in0,data_in1,data_out0,data_out1,CS_0,CS_1,WR,OE,clk,rst);
parameteraddr_width=128;
parameterdata_width=32;
parameter depth=8;
input [addr_width-1:0]addr_0,addr_1;
input [data_width-1:0]data_in0,data_in1;
input CS_0,CS_1,WR,OE,clk,rst;
output [data_width-1:0]data_out0,data_out1;
reg [data_width-1:0]d_out0,d_out1;
reg [data_width-1:0]mem[depth-1:0];
integer i;
always @(posedgeclk)
begin
if(rst)
begin
for(i=0;i<=depth-1;i=i+1)
begin
mem[i]=0;
end
end
else if (CS_0)
begin
if (WR) mem[addr_0]=data_in0;
else d_out0=mem[addr_0];
end
if (CS_1)
begin
if (WR) mem[addr_1]=data_in1;
else d_out1=mem[addr_1];
end
end
assign data_out0=(CS_0 && OE && ~WR) ? d_out0 : 8'hz;
assign data_out1=(CS_1 && OE && ~WR) ? d_out1 : 8'hz;
endmodule