Design a 2-bit Gray code generator that repetitively delivers the sequence 00a01
ID: 2083343 • Letter: D
Question
Design a 2-bit Gray code generator that repetitively delivers the sequence 00a01a11a10a00 rightarrow ellipse when the input signal UP = 1, or in reverse order 00a10a 11a10a00 rightarrow ellipse when UP = 0. Your design should include an asynchronous low-active reset operation: the FSM goes to 00 state when a reset signal is applied. In addition to the state output z[1], z[0], there is a carry/borrow output bit c which is 1 when state=11 and up=1 or when state=00 and up=0. I) Complete the state transition diagram. 2) Write the Verilog program. module graycodecounter2(clock, reset, up, z, c);Explanation / Answer
module toplevel(clock , reset);
input clock;
input reset;
reg flop1;
reg flop2;
always @ (posedge reset or posedge clock)
if (reset)
begin
flop1 <=0;
flop2 <=1;
end
else
begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule