For the following circuit: a.Compute the maximum delay where each NAND gate has

Question

For the following circuit:

a.Compute the maximum delay where each NAND gate has an output rising delay of 2ns and a falling of 1ns. NOR gates are just the opposite and have 1ns rising and 2ns falling delays. NOT gates are 1ns rise, 1ns fall.

i.Assuming that all inputs are available both uncomplemented and complemented.

ii.Assuming only uncomplemented inputs are available and an additional gate must be added to complement each input

b.Compute the maximum delay from input C to the output, assuming that all inputs are available both un-complemented and complemented.

Explanation / Answer

a(i):::::Compute Maximum Delay When both complemented and uncmplemented inputa are available

the deay of individual gate=3ns

there are 1o gates from input to output ,so the total delay =10*3ns=30 ns

(ii):::complemented inputs are not available

there are 10 gates and 4 complemented inputs

so the total delay=10*3ns+4*2ns=38ns

b)Maximum Delay from input C to output

delay=30ns

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