I. Taking a Dim View First your circuit will control the brightness of an LED on
ID: 2249052 • Letter: I
Question
I. Taking a Dim View First your circuit will control the brightness of an LED on the Basys 3 board using simple pulse-width modulation (PWM). The only output from your circuit is fed into a single LED. Run the Clock Wizard to create a slowed clock with a fixed value of 5.00 Mega- the 16 bit R (the duty cycle) be determined by the slide switches. hanging the duty cycle output by the computer should appropriately change the brightness of the LED. Also, generate a copy of the RTL schematic for this solution and save an image for your report..Explanation / Answer
//FPGA IMPLEMENTATION
//verilog code HDL programming for generating PWM signal.
//creation of GUI
input[17:0]SW;
input[3:0]KEY;
input CLOCK_5;
inout[39:0]GPIO_0,GPIO_1;
output[17:0]LEDR;
output[3:0]LEDG;
output[7:0]
HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;integer tenth,unit,fp1,fp2;
integer tentho,unito,fp1o,fp2o;
wire w1,w2,w3,wx;
reg[39:0]GPIO_0,GPIO_1;
reg[17:0]LEDR;
integer count=0;
integer freq=0;
integer a=0;
integer b=0;
interger loop=0;
integer width=0;
integer widtho=0;
//duty cycle for the input signal
SEVEN_SEGseg0(HEX0,fp2);
SEVEN_SEGseg1(HEX1,fp1);
SEVEN_SEGseg2(HEX2,unit);
SEVEN_SEGseg3(HEX3,tenth);
//encoder freq
SEVEN_SEGseg4(HEX4,fp2o);
SEVEN_SEGseg5(HEX5,fp1o);
SEVEN_SEGseg6(HEX6,unito);
SEVEN_SEGseg7(HEX7,tentho);
always
begin
Tenth=(width-width%1000)/1000;
Unit=(width-width%100-tenth*1000)/100;
fp1=(width-width%10-1000*tenth-100*unit)/10;
fp2=(width-1000*tenth-100*unit-10*fp1);
End
always
begin
Tentho=(widtho-widtho%1000)/1000;
Unito=(widtho-widtho%100-tentho*1000)/100;
fp1o=(widtho-widtho%10-1000*tentho-100*unito)/10;
fp2o=(widtho-1000*tentho-100*unito-10*fp1o);
End
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