Civen ine state transition dacram below diacyram lelow Macn.ne?ogram)CS0/100 (Fi
ID: 2292075 • Letter: C
Question
Civen ine state transition dacram below diacyram lelow Macn.ne?ogram)CS0/100 (Finite State 0/0 1/0 1/0 1/0 So S2 /0 S3 1. For VHDL implementation, fill the blank space to complete the code. (23 points) library ieee; use ieee.std_logic_1164.all; entity final is port clk :in std_logic; X :in std logic; Y out std_logic); end entity architecture FSM of type stateType is (s0, s1, s2, s3); signal currentState signal nextState: begin 1S := sO process(currentState) begin case( )is when s0 => if X '0' then nextStateExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity final is
Port ( clk : in std_logic;
x : in std_logic;
y : out std_logic);
end entity;
architecture FSM of final is
type stateType is (s0,s1,s2,s3);
signal currentstate: stateType :=s0;
signal nextstate: stateType;
begin
process(currentstate)
begin
case (currentstate) is
when S0 =>
if X='0' then nextstate<= s0; y<='0'; elsif X='1' then nextstate<= s1; y<='0'; end if;
when S1 =>
if X='0' then nextstate<= s3; y<='0'; elsif X='1' then nextstate<= s2; y<='0';end if;
when S2 =>
if X='0' then nextstate<= s3; y<='1'; elsif X='1' then nextstate<= s2; y<='0';end if;
when S3 =>
if X='0' then nextstate<= s0; y<='0'; elsif X='1' then nextstate<= s1; y<='1'; end if;
end case;
end process;
end FSM;