Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses f
ID: 2314079 • Letter: C
Question
Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses four Toggle flip-flops. The counter increments its count on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by using the (asynchronous) Reset signal. You are to implement a 16-bit counter of this type. Figure 1. A 4-bit counter. Write a VHDL file that defines a 16-bit counter by using the structure depicted in Figure 1, and compile the circuit. Look at your Compilation Report, under Timing Analyzer. What is the maximum frequency, F_max, at which your circuit can be operated?Explanation / Answer
First define the T flip-flop entity and use it as component in the structural design.
entity T_ff is,
port(T,Clock,Clear: in std_logic;
Q:out std_logic);
end T_ff;
architecture arc_T_ff of T_ff is,
signal Q_temp: std_logic;
begin
process(Clock)
begin
if Clear ==’1’ then Q_temp<=0;
elsif clk’event and clk=’1’ then
if T=1 then Q_temp<=not Q_temp;
else
Q_temp<=Q_temp;
end
end
end
end arc_T_ff;
Use T_ff component and write the structural code for the 4-bit synchronous counter.
entity syn_counter is,
port(T,Clock,Enable,Clear: in std_logic;
Q:out std_logic_vector (3 downto 0);
end syn_counter;
architecture arc_ syn_counter of syn_counter is,
signal temp1,temp2,temp3, E1,E2,E3: std_logic;
component T_ff
port(T,Clock,Clear: in std_logic;
Q:out std_logic);
end component;
T1: T_ff port map(Enable,Clock,Clear,temp1);
E1<=temp1 and Enable;
T2: T_ff port map(E1,Clock,clear,temp2);
E2<=temp2 and E1;
T3: T_ff port map(E2,Clock,clear,temp3);
E3<=temp3 and E2;
T4: T_ff port map(E3,Clock,clear,temp4);
Q<=temp1& temp2& temp3& temp4;
end arc_ syn_counter;